[PATCH] D150671: RISCV/InstrInfo: model register pressure for MICombiner

Kito Cheng via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Jun 2 06:40:39 PDT 2023


kito-cheng added a comment.

Does here some benchmark result on this change? I guess small benchmarks like dhrystone or coremark might not changed at all, so maybe spec cpu?



================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:1412
+
+  LLVM_DEBUG(dbgs() << "Register Pressure: " << Pressure << "::" << GPRLimit
+                    << "\n");
----------------
Mention it's GPR class in debug info


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:1613
 
+  if (DoRegPressureReduce)
+    return false;
----------------
I would like to have few more comment to mention we are only tracking reg pressure on GPR here.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D150671/new/

https://reviews.llvm.org/D150671



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