[PATCH] D151894: [AArch64] Neoverse V2 scheduling model

[Graham Hunter via Phabricator via llvm-commits]

huntergr added a comment.

Thanks for working on this.

I'm not sure how much difference the 'F' vs 'I' pipeline restrictions matter in practice, but I've spotted a few cases where the model will use 'I' instead of the more restrictive 'F'



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Comment at: llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td:985
+// ALU, basic, flagset
+def : SchedAlias<WriteI,     V2Write_1cyc_1I>;
+
----------------
The flag setting variants use the 'F' pipelines rather than 'I'. The others do use 'I' though, so perhaps a predicate would work here.


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Comment at: llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td:993
+// Arithmetic, LSR/ASR/ROR shift or LSL shift > 4
+def : SchedAlias<WriteISReg, V2Write_Arith>;
+
----------------
Same issue with single-cycle flag setting variants using 'F' pipelines.


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Comment at: llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td:1015
+// Logical, shift, flagset
+def : InstRW<[V2Write_Logical], (instregex "^(AND|BIC)S[WX]rs$")>;
+
----------------
These also use the 'F' pipelines in the NOLSL case.


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  https://reviews.llvm.org/D151894/new/

https://reviews.llvm.org/D151894