[PATCH] D76007: [TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes

[Nitin John Raj via Phabricator via llvm-commits]

nitinjohnraj updated this revision to Diff 527691.
nitinjohnraj added a comment.

Use `DefaultMode` instead of 0.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D76007/new/

https://reviews.llvm.org/D76007

Files:
  llvm/include/llvm/CodeGen/RegisterBank.h
  llvm/include/llvm/CodeGen/RegisterBankInfo.h
  llvm/lib/CodeGen/MachineVerifier.cpp
  llvm/lib/CodeGen/RegisterBank.cpp
  llvm/lib/CodeGen/RegisterBankInfo.cpp
  llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
  llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
  llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
  llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.h
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/lib/Target/X86/X86RegisterBankInfo.cpp
  llvm/utils/TableGen/RegisterBankEmitter.cpp

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