[llvm] 37cfcfc - [RISCV] Separate slideup/down pseudoinstructions from FMA instructions earlier in the class hierarchy.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-06-01T15:25:40-07:00
New Revision: 37cfcfcef76bb615b941d7077ca81168bd7ad080

URL: https://github.com/llvm/llvm-project/commit/37cfcfcef76bb615b941d7077ca81168bd7ad080
DIFF: https://github.com/llvm/llvm-project/commit/37cfcfcef76bb615b941d7077ca81168bd7ad080.diff

LOG: [RISCV] Separate slideup/down pseudoinstructions from FMA instructions earlier in the class hierarchy.

Remove RISCVMaskedPseudo from vslideup/down. I hadn't intended to
include them. I missed that they used the same classes as FMA.
They weren't tested and I don't have a use case yet.

This is also needed as I attempt refactor the classes to improve
D151850.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index eb18e38e5302..aa2965626303 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -3245,12 +3245,23 @@ multiclass VPseudoTernaryW_VF<LMULInfo m, FPR_Info f> {
                                               m.vrclass, m, constraint>;
 }
 
+multiclass VPseudoVSLDVWithPolicy<VReg RetClass,
+                                  RegisterClass Op1Class,
+                                  DAGOperand Op2Class,
+                                  LMULInfo MInfo,
+                                  string Constraint = ""> {
+  let VLMul = MInfo.value in {
+    def "_" # MInfo.MX : VPseudoTernaryNoMaskWithPolicy<RetClass, Op1Class, Op2Class, Constraint>;
+    def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class, Constraint>;
+  }
+}
+
 multiclass VPseudoVSLDV_VX<LMULInfo m, string Constraint = ""> {
-  defm _VX : VPseudoTernaryWithPolicy<m.vrclass, m.vrclass, GPR, m, Constraint>;
+  defm _VX : VPseudoVSLDVWithPolicy<m.vrclass, m.vrclass, GPR, m, Constraint>;
 }
 
 multiclass VPseudoVSLDV_VI<Operand ImmType = simm5, LMULInfo m, string Constraint = ""> {
-  defm _VI : VPseudoTernaryWithPolicy<m.vrclass, m.vrclass, ImmType, m, Constraint>;
+  defm _VI : VPseudoVSLDVWithPolicy<m.vrclass, m.vrclass, ImmType, m, Constraint>;
 }
 
 multiclass VPseudoVMAC_VV_VX_AAXA<string Constraint = ""> {