[llvm] 5022fc2 - [CodeGen] Make use of MachineInstr::all_defs and all_uses. NFCI.
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 1 11:21:08 PDT 2023
Author: Jay Foad
Date: 2023-06-01T19:17:34+01:00
New Revision: 5022fc2ad31b5e3211e2458347c89412b8c5ec1b
URL: https://github.com/llvm/llvm-project/commit/5022fc2ad31b5e3211e2458347c89412b8c5ec1b
DIFF: https://github.com/llvm/llvm-project/commit/5022fc2ad31b5e3211e2458347c89412b8c5ec1b.diff
LOG: [CodeGen] Make use of MachineInstr::all_defs and all_uses. NFCI.
Differential Revision: https://reviews.llvm.org/D151424
Added:
Modified:
llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp
llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
llvm/lib/CodeGen/BranchFolding.cpp
llvm/lib/CodeGen/BreakFalseDeps.cpp
llvm/lib/CodeGen/DeadMachineInstructionElim.cpp
llvm/lib/CodeGen/GlobalISel/Utils.cpp
llvm/lib/CodeGen/ImplicitNullChecks.cpp
llvm/lib/CodeGen/InlineSpiller.cpp
llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp
llvm/lib/CodeGen/LiveVariables.cpp
llvm/lib/CodeGen/MachineBasicBlock.cpp
llvm/lib/CodeGen/MachineCSE.cpp
llvm/lib/CodeGen/MachineCombiner.cpp
llvm/lib/CodeGen/MachineDebugify.cpp
llvm/lib/CodeGen/MachineFunction.cpp
llvm/lib/CodeGen/MachineLICM.cpp
llvm/lib/CodeGen/MachinePipeliner.cpp
llvm/lib/CodeGen/MachineSSAContext.cpp
llvm/lib/CodeGen/MachineScheduler.cpp
llvm/lib/CodeGen/MachineSink.cpp
llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
llvm/lib/CodeGen/ModuloSchedule.cpp
llvm/lib/CodeGen/ProcessImplicitDefs.cpp
llvm/lib/CodeGen/RDFGraph.cpp
llvm/lib/CodeGen/RDFLiveness.cpp
llvm/lib/CodeGen/RegAllocFast.cpp
llvm/lib/CodeGen/RegisterCoalescer.cpp
llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp b/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp
index 3c24e81b935ce..886c4db069f14 100644
--- a/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp
+++ b/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp
@@ -351,8 +351,7 @@ void AggressiveAntiDepBreaker::PrescanInstruction(
// dead, or because only a subregister is live at the def. If we
// don't do this the dead def will be incorrectly merged into the
// previous def.
- for (const MachineOperand &MO : MI.operands()) {
- if (!MO.isReg() || !MO.isDef()) continue;
+ for (const MachineOperand &MO : MI.all_defs()) {
Register Reg = MO.getReg();
if (Reg == 0) continue;
diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
index a24e6e2e99229..e0814c0f61af6 100644
--- a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
@@ -707,8 +707,8 @@ static void interpretValues(const MachineInstr *CurMI,
if (MI.isDebugInstr())
return;
- for (const MachineOperand &MO : MI.operands()) {
- if (MO.isReg() && MO.isDef() && MO.getReg().isPhysical()) {
+ for (const MachineOperand &MO : MI.all_defs()) {
+ if (MO.getReg().isPhysical()) {
for (auto &FwdReg : ForwardedRegWorklist)
if (TRI.regsOverlap(FwdReg.first, MO.getReg()))
Defs.insert(FwdReg.first);
diff --git a/llvm/lib/CodeGen/BranchFolding.cpp b/llvm/lib/CodeGen/BranchFolding.cpp
index a5302a66d21e5..3830f25debaf3 100644
--- a/llvm/lib/CodeGen/BranchFolding.cpp
+++ b/llvm/lib/CodeGen/BranchFolding.cpp
@@ -1997,8 +1997,8 @@ bool BranchFolder::HoistCommonCodeInSuccs(MachineBasicBlock *MBB) {
break;
// Remove kills from ActiveDefsSet, these registers had short live ranges.
- for (const MachineOperand &MO : TIB->operands()) {
- if (!MO.isReg() || !MO.isUse() || !MO.isKill())
+ for (const MachineOperand &MO : TIB->all_uses()) {
+ if (!MO.isKill())
continue;
Register Reg = MO.getReg();
if (!Reg)
@@ -2015,8 +2015,8 @@ bool BranchFolder::HoistCommonCodeInSuccs(MachineBasicBlock *MBB) {
}
// Track local defs so we can update liveins.
- for (const MachineOperand &MO : TIB->operands()) {
- if (!MO.isReg() || !MO.isDef() || MO.isDead())
+ for (const MachineOperand &MO : TIB->all_defs()) {
+ if (MO.isDead())
continue;
Register Reg = MO.getReg();
if (!Reg || Reg.isVirtual())
diff --git a/llvm/lib/CodeGen/BreakFalseDeps.cpp b/llvm/lib/CodeGen/BreakFalseDeps.cpp
index 96945428c41fe..9789381f7601a 100644
--- a/llvm/lib/CodeGen/BreakFalseDeps.cpp
+++ b/llvm/lib/CodeGen/BreakFalseDeps.cpp
@@ -140,9 +140,8 @@ bool BreakFalseDeps::pickBestRegisterForUndef(MachineInstr *MI, unsigned OpIdx,
// If the instruction has a true dependency, we can hide the false depdency
// behind it.
- for (MachineOperand &CurrMO : MI->operands()) {
- if (!CurrMO.isReg() || CurrMO.isDef() || CurrMO.isUndef() ||
- !OpRC->contains(CurrMO.getReg()))
+ for (MachineOperand &CurrMO : MI->all_uses()) {
+ if (CurrMO.isUndef() || !OpRC->contains(CurrMO.getReg()))
continue;
// We found a true dependency - replace the undef register with the true
// dependency.
diff --git a/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp b/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp
index 5fc1897dd2224..6a7de3b241fee 100644
--- a/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp
+++ b/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp
@@ -75,27 +75,25 @@ bool DeadMachineInstructionElim::isDead(const MachineInstr *MI) const {
return false;
// Examine each operand.
- for (const MachineOperand &MO : MI->operands()) {
- if (MO.isReg() && MO.isDef()) {
- Register Reg = MO.getReg();
- if (Reg.isPhysical()) {
- // Don't delete live physreg defs, or any reserved register defs.
- if (!LivePhysRegs.available(Reg) || MRI->isReserved(Reg))
- return false;
- } else {
- if (MO.isDead()) {
+ for (const MachineOperand &MO : MI->all_defs()) {
+ Register Reg = MO.getReg();
+ if (Reg.isPhysical()) {
+ // Don't delete live physreg defs, or any reserved register defs.
+ if (!LivePhysRegs.available(Reg) || MRI->isReserved(Reg))
+ return false;
+ } else {
+ if (MO.isDead()) {
#ifndef NDEBUG
- // Basic check on the register. All of them should be 'undef'.
- for (auto &U : MRI->use_nodbg_operands(Reg))
- assert(U.isUndef() && "'Undef' use on a 'dead' register is found!");
+ // Basic check on the register. All of them should be 'undef'.
+ for (auto &U : MRI->use_nodbg_operands(Reg))
+ assert(U.isUndef() && "'Undef' use on a 'dead' register is found!");
#endif
- continue;
- }
- for (const MachineInstr &Use : MRI->use_nodbg_instructions(Reg)) {
- if (&Use != MI)
- // This def has a non-debug use. Don't delete the instruction!
- return false;
- }
+ continue;
+ }
+ for (const MachineInstr &Use : MRI->use_nodbg_instructions(Reg)) {
+ if (&Use != MI)
+ // This def has a non-debug use. Don't delete the instruction!
+ return false;
}
}
}
diff --git a/llvm/lib/CodeGen/GlobalISel/Utils.cpp b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
index fb47832bc5fb8..080600d3cc986 100644
--- a/llvm/lib/CodeGen/GlobalISel/Utils.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
@@ -230,10 +230,7 @@ bool llvm::isTriviallyDead(const MachineInstr &MI,
return false;
// Instructions without side-effects are dead iff they only define dead vregs.
- for (const auto &MO : MI.operands()) {
- if (!MO.isReg() || !MO.isDef())
- continue;
-
+ for (const auto &MO : MI.all_defs()) {
Register Reg = MO.getReg();
if (Reg.isPhysical() || !MRI.use_nodbg_empty(Reg))
return false;
diff --git a/llvm/lib/CodeGen/ImplicitNullChecks.cpp b/llvm/lib/CodeGen/ImplicitNullChecks.cpp
index ae002e074add2..b2a7aad734115 100644
--- a/llvm/lib/CodeGen/ImplicitNullChecks.cpp
+++ b/llvm/lib/CodeGen/ImplicitNullChecks.cpp
@@ -778,9 +778,7 @@ void ImplicitNullChecks::rewriteNullChecks(
// The original operation may define implicit-defs alongside
// the value.
MachineBasicBlock *MBB = NC.getMemOperation()->getParent();
- for (const MachineOperand &MO : FaultingInstr->operands()) {
- if (!MO.isReg() || !MO.isDef())
- continue;
+ for (const MachineOperand &MO : FaultingInstr->all_defs()) {
Register Reg = MO.getReg();
if (!Reg || MBB->isLiveIn(Reg))
continue;
@@ -788,8 +786,8 @@ void ImplicitNullChecks::rewriteNullChecks(
}
if (auto *DepMI = NC.getOnlyDependency()) {
- for (auto &MO : DepMI->operands()) {
- if (!MO.isReg() || !MO.getReg() || !MO.isDef() || MO.isDead())
+ for (auto &MO : DepMI->all_defs()) {
+ if (!MO.getReg() || MO.isDead())
continue;
if (!NC.getNotNullSucc()->isLiveIn(MO.getReg()))
NC.getNotNullSucc()->addLiveIn(MO.getReg());
diff --git a/llvm/lib/CodeGen/InlineSpiller.cpp b/llvm/lib/CodeGen/InlineSpiller.cpp
index 1c0926a05958e..01b0dad2f779d 100644
--- a/llvm/lib/CodeGen/InlineSpiller.cpp
+++ b/llvm/lib/CodeGen/InlineSpiller.cpp
@@ -268,8 +268,8 @@ static Register isFullCopyOf(const MachineInstr &MI, Register Reg) {
}
static void getVDefInterval(const MachineInstr &MI, LiveIntervals &LIS) {
- for (const MachineOperand &MO : MI.operands())
- if (MO.isReg() && MO.isDef() && MO.getReg().isVirtual())
+ for (const MachineOperand &MO : MI.all_defs())
+ if (MO.getReg().isVirtual())
LIS.getInterval(MO.getReg());
}
@@ -593,8 +593,8 @@ bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg, MachineInstr &MI) {
if (!ParentVNI) {
LLVM_DEBUG(dbgs() << "\tadding <undef> flags: ");
- for (MachineOperand &MO : MI.operands())
- if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg())
+ for (MachineOperand &MO : MI.all_uses())
+ if (MO.getReg() == VirtReg.reg())
MO.setIsUndef();
LLVM_DEBUG(dbgs() << UseIdx << '\t' << MI);
return true;
diff --git a/llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp b/llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp
index 8aa980794bc09..116c6b7e2d19e 100644
--- a/llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp
+++ b/llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp
@@ -2162,8 +2162,8 @@ bool VarLocBasedLDV::isEntryValueCandidate(
/// Collect all register defines (including aliases) for the given instruction.
static void collectRegDefs(const MachineInstr &MI, DefinedRegsSet &Regs,
const TargetRegisterInfo *TRI) {
- for (const MachineOperand &MO : MI.operands()) {
- if (MO.isReg() && MO.isDef() && MO.getReg() && MO.getReg().isPhysical()) {
+ for (const MachineOperand &MO : MI.all_defs()) {
+ if (MO.getReg() && MO.getReg().isPhysical()) {
Regs.insert(MO.getReg());
for (MCRegAliasIterator AI(MO.getReg(), TRI, true); AI.isValid(); ++AI)
Regs.insert(*AI);
diff --git a/llvm/lib/CodeGen/LiveVariables.cpp b/llvm/lib/CodeGen/LiveVariables.cpp
index 17c1aa093bdcb..9cd74689ba10b 100644
--- a/llvm/lib/CodeGen/LiveVariables.cpp
+++ b/llvm/lib/CodeGen/LiveVariables.cpp
@@ -207,8 +207,8 @@ LiveVariables::FindLastPartialDef(Register Reg,
return nullptr;
PartDefRegs.insert(LastDefReg);
- for (MachineOperand &MO : LastDef->operands()) {
- if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
+ for (MachineOperand &MO : LastDef->all_defs()) {
+ if (MO.getReg() == 0)
continue;
Register DefReg = MO.getReg();
if (TRI->isSubRegister(Reg, DefReg)) {
diff --git a/llvm/lib/CodeGen/MachineBasicBlock.cpp b/llvm/lib/CodeGen/MachineBasicBlock.cpp
index 6a1d5eea51341..3d489e317c0d2 100644
--- a/llvm/lib/CodeGen/MachineBasicBlock.cpp
+++ b/llvm/lib/CodeGen/MachineBasicBlock.cpp
@@ -1130,9 +1130,8 @@ MachineBasicBlock *MachineBasicBlock::SplitCriticalEdge(
if (LV)
for (MachineInstr &MI :
llvm::make_range(getFirstInstrTerminator(), instr_end())) {
- for (MachineOperand &MO : MI.operands()) {
- if (!MO.isReg() || MO.getReg() == 0 || !MO.isUse() || !MO.isKill() ||
- MO.isUndef())
+ for (MachineOperand &MO : MI.all_uses()) {
+ if (MO.getReg() == 0 || !MO.isKill() || MO.isUndef())
continue;
Register Reg = MO.getReg();
if (Reg.isPhysical() || LV->getVarInfo(Reg).removeKill(MI)) {
diff --git a/llvm/lib/CodeGen/MachineCSE.cpp b/llvm/lib/CodeGen/MachineCSE.cpp
index 03e69f83d5e7e..f879c5fcf20c9 100644
--- a/llvm/lib/CodeGen/MachineCSE.cpp
+++ b/llvm/lib/CodeGen/MachineCSE.cpp
@@ -175,9 +175,7 @@ INITIALIZE_PASS_END(MachineCSE, DEBUG_TYPE,
bool MachineCSE::PerformTrivialCopyPropagation(MachineInstr *MI,
MachineBasicBlock *MBB) {
bool Changed = false;
- for (MachineOperand &MO : MI->operands()) {
- if (!MO.isReg() || !MO.isUse())
- continue;
+ for (MachineOperand &MO : MI->all_uses()) {
Register Reg = MO.getReg();
if (!Reg.isVirtual())
continue;
@@ -291,9 +289,7 @@ bool MachineCSE::hasLivePhysRegDefUses(const MachineInstr *MI,
PhysDefVector &PhysDefs,
bool &PhysUseDef) const {
// First, add all uses to PhysRefs.
- for (const MachineOperand &MO : MI->operands()) {
- if (!MO.isReg() || MO.isDef())
- continue;
+ for (const MachineOperand &MO : MI->all_uses()) {
Register Reg = MO.getReg();
if (!Reg)
continue;
@@ -483,8 +479,8 @@ bool MachineCSE::isProfitableToCSE(Register CSReg, Register Reg,
// Heuristics #2: If the expression doesn't not use a vr and the only use
// of the redundant computation are copies, do not cse.
bool HasVRegUse = false;
- for (const MachineOperand &MO : MI->operands()) {
- if (MO.isReg() && MO.isUse() && MO.getReg().isVirtual()) {
+ for (const MachineOperand &MO : MI->all_uses()) {
+ if (MO.getReg().isVirtual()) {
HasVRegUse = true;
break;
}
diff --git a/llvm/lib/CodeGen/MachineCombiner.cpp b/llvm/lib/CodeGen/MachineCombiner.cpp
index ec5eb71205cf1..c65937935ed82 100644
--- a/llvm/lib/CodeGen/MachineCombiner.cpp
+++ b/llvm/lib/CodeGen/MachineCombiner.cpp
@@ -217,11 +217,9 @@ MachineCombiner::getDepth(SmallVectorImpl<MachineInstr *> &InsInstrs,
// are tracked in the InstrIdxForVirtReg map depth is looked up in InstrDepth
for (auto *InstrPtr : InsInstrs) { // for each Use
unsigned IDepth = 0;
- for (const MachineOperand &MO : InstrPtr->operands()) {
+ for (const MachineOperand &MO : InstrPtr->all_uses()) {
// Check for virtual register operand.
- if (!(MO.isReg() && MO.getReg().isVirtual()))
- continue;
- if (!MO.isUse())
+ if (!MO.getReg().isVirtual())
continue;
unsigned DepthOp = 0;
unsigned LatencyOp = 0;
@@ -272,11 +270,9 @@ unsigned MachineCombiner::getLatency(MachineInstr *Root, MachineInstr *NewRoot,
// Check each definition in NewRoot and compute the latency
unsigned NewRootLatency = 0;
- for (const MachineOperand &MO : NewRoot->operands()) {
+ for (const MachineOperand &MO : NewRoot->all_defs()) {
// Check for virtual register operand.
- if (!(MO.isReg() && MO.getReg().isVirtual()))
- continue;
- if (!MO.isDef())
+ if (!MO.getReg().isVirtual())
continue;
// Get the first instruction that uses MO
MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(MO.getReg());
diff --git a/llvm/lib/CodeGen/MachineDebugify.cpp b/llvm/lib/CodeGen/MachineDebugify.cpp
index adf1b51a950d8..c264e199cf472 100644
--- a/llvm/lib/CodeGen/MachineDebugify.cpp
+++ b/llvm/lib/CodeGen/MachineDebugify.cpp
@@ -116,8 +116,8 @@ bool applyDebugifyMetadataToMachineFunction(MachineModuleInfo &MMI,
// Emit DBG_VALUEs for register definitions.
SmallVector<MachineOperand *, 4> RegDefs;
- for (MachineOperand &MO : MI.operands())
- if (MO.isReg() && MO.isDef() && MO.getReg())
+ for (MachineOperand &MO : MI.all_defs())
+ if (MO.getReg())
RegDefs.push_back(&MO);
for (MachineOperand *MO : RegDefs)
BuildMI(MBB, InsertBeforeIt, MI.getDebugLoc(), DbgValDesc,
diff --git a/llvm/lib/CodeGen/MachineFunction.cpp b/llvm/lib/CodeGen/MachineFunction.cpp
index b33bb45e60136..e1cf41749608c 100644
--- a/llvm/lib/CodeGen/MachineFunction.cpp
+++ b/llvm/lib/CodeGen/MachineFunction.cpp
@@ -1082,8 +1082,8 @@ auto MachineFunction::salvageCopySSAImpl(MachineInstr &MI)
if (State.first.isVirtual()) {
// Virtual register def -- we can just look up where this happens.
MachineInstr *Inst = MRI.def_begin(State.first)->getParent();
- for (auto &MO : Inst->operands()) {
- if (!MO.isReg() || !MO.isDef() || MO.getReg() != State.first)
+ for (auto &MO : Inst->all_defs()) {
+ if (MO.getReg() != State.first)
continue;
return ApplySubregisters({Inst->getDebugInstrNum(), MO.getOperandNo()});
}
@@ -1100,10 +1100,9 @@ auto MachineFunction::salvageCopySSAImpl(MachineInstr &MI)
auto RMII = CurInst->getReverseIterator();
auto PrevInstrs = make_range(RMII, CurInst->getParent()->instr_rend());
for (auto &ToExamine : PrevInstrs) {
- for (auto &MO : ToExamine.operands()) {
+ for (auto &MO : ToExamine.all_defs()) {
// Test for operand that defines something aliasing RegToSeek.
- if (!MO.isReg() || !MO.isDef() ||
- !TRI.regsOverlap(RegToSeek, MO.getReg()))
+ if (!TRI.regsOverlap(RegToSeek, MO.getReg()))
continue;
return ApplySubregisters(
diff --git a/llvm/lib/CodeGen/MachineLICM.cpp b/llvm/lib/CodeGen/MachineLICM.cpp
index 93870e815250a..4e80e9b58c060 100644
--- a/llvm/lib/CodeGen/MachineLICM.cpp
+++ b/llvm/lib/CodeGen/MachineLICM.cpp
@@ -575,8 +575,8 @@ void MachineLICMBase::HoistRegionPostRA() {
if (!PhysRegClobbers.test(Def) && !TermRegs.test(Def)) {
bool Safe = true;
MachineInstr *MI = Candidate.MI;
- for (const MachineOperand &MO : MI->operands()) {
- if (!MO.isReg() || MO.isDef() || !MO.getReg())
+ for (const MachineOperand &MO : MI->all_uses()) {
+ if (!MO.getReg())
continue;
Register Reg = MO.getReg();
if (PhysRegDefs.test(Reg) ||
@@ -600,8 +600,9 @@ void MachineLICMBase::AddToLiveIns(MCRegister Reg) {
if (!BB->isLiveIn(Reg))
BB->addLiveIn(Reg);
for (MachineInstr &MI : *BB) {
- for (MachineOperand &MO : MI.operands()) {
- if (!MO.isReg() || !MO.getReg() || MO.isDef()) continue;
+ for (MachineOperand &MO : MI.all_uses()) {
+ if (!MO.getReg())
+ continue;
if (MO.getReg() == Reg || TRI->isSuperRegister(Reg, MO.getReg()))
MO.setIsKill(false);
}
@@ -669,8 +670,8 @@ bool MachineLICMBase::isTriviallyReMaterializable(
if (!TII->isTriviallyReMaterializable(MI))
return false;
- for (const MachineOperand &MO : MI.operands()) {
- if (MO.isReg() && MO.isUse() && MO.getReg().isVirtual())
+ for (const MachineOperand &MO : MI.all_uses()) {
+ if (MO.getReg().isVirtual())
return false;
}
@@ -1014,9 +1015,7 @@ bool MachineLICMBase::HasLoopPHIUse(const MachineInstr *MI) const {
SmallVector<const MachineInstr*, 8> Work(1, MI);
do {
MI = Work.pop_back_val();
- for (const MachineOperand &MO : MI->operands()) {
- if (!MO.isReg() || !MO.isDef())
- continue;
+ for (const MachineOperand &MO : MI->all_defs()) {
Register Reg = MO.getReg();
if (!Reg.isVirtual())
continue;
@@ -1455,8 +1454,8 @@ bool MachineLICMBase::Hoist(MachineInstr *MI, MachineBasicBlock *Preheader) {
// Clear the kill flags of any register this instruction defines,
// since they may need to be live throughout the entire loop
// rather than just live for part of it.
- for (MachineOperand &MO : MI->operands())
- if (MO.isReg() && MO.isDef() && !MO.isDead())
+ for (MachineOperand &MO : MI->all_defs())
+ if (!MO.isDead())
MRI->clearKillFlags(MO.getReg());
// Add to the CSE map.
diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp
index dbdae987b3428..3f9fbb7e20297 100644
--- a/llvm/lib/CodeGen/MachinePipeliner.cpp
+++ b/llvm/lib/CodeGen/MachinePipeliner.cpp
@@ -1557,20 +1557,19 @@ static void computeLiveOuts(MachineFunction &MF, RegPressureTracker &RPTracker,
const MachineInstr *MI = SU->getInstr();
if (MI->isPHI())
continue;
- for (const MachineOperand &MO : MI->operands())
- if (MO.isReg() && MO.isUse()) {
- Register Reg = MO.getReg();
- if (Reg.isVirtual())
- Uses.insert(Reg);
- else if (MRI.isAllocatable(Reg))
- for (MCRegUnitIterator Units(Reg.asMCReg(), TRI); Units.isValid();
- ++Units)
- Uses.insert(*Units);
- }
+ for (const MachineOperand &MO : MI->all_uses()) {
+ Register Reg = MO.getReg();
+ if (Reg.isVirtual())
+ Uses.insert(Reg);
+ else if (MRI.isAllocatable(Reg))
+ for (MCRegUnitIterator Units(Reg.asMCReg(), TRI); Units.isValid();
+ ++Units)
+ Uses.insert(*Units);
+ }
}
for (SUnit *SU : NS)
- for (const MachineOperand &MO : SU->getInstr()->operands())
- if (MO.isReg() && MO.isDef() && !MO.isDead()) {
+ for (const MachineOperand &MO : SU->getInstr()->all_defs())
+ if (!MO.isDead()) {
Register Reg = MO.getReg();
if (Reg.isVirtual()) {
if (!Uses.count(Reg))
@@ -2652,9 +2651,7 @@ bool SMSchedule::isLoopCarriedDefOfUse(SwingSchedulerDAG *SSD,
if (!isLoopCarried(SSD, *Phi))
return false;
unsigned LoopReg = getLoopPhiReg(*Phi, Phi->getParent());
- for (MachineOperand &DMO : Def->operands()) {
- if (!DMO.isReg() || !DMO.isDef())
- continue;
+ for (MachineOperand &DMO : Def->all_defs()) {
if (DMO.getReg() == LoopReg)
return true;
}
diff --git a/llvm/lib/CodeGen/MachineSSAContext.cpp b/llvm/lib/CodeGen/MachineSSAContext.cpp
index 7e53ce4d68615..f7d43a510a58d 100644
--- a/llvm/lib/CodeGen/MachineSSAContext.cpp
+++ b/llvm/lib/CodeGen/MachineSSAContext.cpp
@@ -42,10 +42,8 @@ void MachineSSAContext::appendBlockTerms(
void MachineSSAContext::appendBlockDefs(SmallVectorImpl<Register> &defs,
const MachineBasicBlock &block) {
for (const MachineInstr &instr : block.instrs()) {
- for (const MachineOperand &op : instr.operands()) {
- if (op.isReg() && op.isDef())
- defs.push_back(op.getReg());
- }
+ for (const MachineOperand &op : instr.all_defs())
+ defs.push_back(op.getReg());
}
}
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index 3fa35d7c43320..b5b91802ef238 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -1127,8 +1127,8 @@ void ScheduleDAGMILive::collectVRegUses(SUnit &SU) {
// Ignore re-defs.
if (TrackLaneMasks) {
bool FoundDef = false;
- for (const MachineOperand &MO2 : MI.operands()) {
- if (MO2.isReg() && MO2.isDef() && MO2.getReg() == Reg && !MO2.isDead()) {
+ for (const MachineOperand &MO2 : MI.all_defs()) {
+ if (MO2.getReg() == Reg && !MO2.isDead()) {
FoundDef = true;
break;
}
diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp
index 1bd370584fadb..e18a19e785b04 100644
--- a/llvm/lib/CodeGen/MachineSink.cpp
+++ b/llvm/lib/CodeGen/MachineSink.cpp
@@ -602,9 +602,7 @@ bool MachineSinking::isWorthBreakingCriticalEdge(MachineInstr &MI,
// MI is cheap, we probably don't want to break the critical edge for it.
// However, if this would allow some definitions of its source operands
// to be sunk then it's probably worth it.
- for (const MachineOperand &MO : MI.operands()) {
- if (!MO.isReg() || !MO.isUse())
- continue;
+ for (const MachineOperand &MO : MI.all_uses()) {
Register Reg = MO.getReg();
if (Reg == 0)
continue;
@@ -1381,9 +1379,7 @@ bool MachineSinking::SinkInstruction(MachineInstr &MI, bool &SawStore,
// If the instruction to move defines a dead physical register which is live
// when leaving the basic block, don't move it because it could turn into a
// "zombie" define of that preg. E.g., EFLAGS. (<rdar://problem/8030636>)
- for (const MachineOperand &MO : MI.operands()) {
- if (!MO.isReg() || MO.isUse())
- continue;
+ for (const MachineOperand &MO : MI.all_defs()) {
Register Reg = MO.getReg();
if (Reg == 0 || !Reg.isPhysical())
continue;
@@ -1461,8 +1457,8 @@ bool MachineSinking::SinkInstruction(MachineInstr &MI, bool &SawStore,
// Collect debug users of any vreg that this inst defines.
SmallVector<MIRegs, 4> DbgUsersToSink;
- for (auto &MO : MI.operands()) {
- if (!MO.isReg() || !MO.isDef() || !MO.getReg().isVirtual())
+ for (auto &MO : MI.all_defs()) {
+ if (!MO.getReg().isVirtual())
continue;
if (!SeenDbgUsers.count(MO.getReg()))
continue;
@@ -1496,10 +1492,8 @@ bool MachineSinking::SinkInstruction(MachineInstr &MI, bool &SawStore,
// Note that we have to clear the kill flags for any register this instruction
// uses as we may sink over another instruction which currently kills the
// used registers.
- for (MachineOperand &MO : MI.operands()) {
- if (MO.isReg() && MO.isUse())
- RegsToClearKillFlags.insert(MO.getReg()); // Remember to clear kill flags.
- }
+ for (MachineOperand &MO : MI.all_uses())
+ RegsToClearKillFlags.insert(MO.getReg()); // Remember to clear kill flags.
return true;
}
@@ -1515,8 +1509,8 @@ void MachineSinking::SalvageUnsunkDebugUsersOfCopy(
SmallVector<MachineInstr *, 4> DbgDefUsers;
SmallVector<Register, 4> DbgUseRegs;
const MachineRegisterInfo &MRI = MI.getMF()->getRegInfo();
- for (auto &MO : MI.operands()) {
- if (!MO.isReg() || !MO.isDef() || !MO.getReg().isVirtual())
+ for (auto &MO : MI.all_defs()) {
+ if (!MO.getReg().isVirtual())
continue;
DbgUseRegs.push_back(MO.getReg());
for (auto &User : MRI.use_instructions(MO.getReg())) {
@@ -1842,10 +1836,7 @@ bool PostRAMachineSinking::tryToSinkCopy(MachineBasicBlock &CurBB,
// recorded which reg units that DBG_VALUEs read, if this instruction
// writes any of those units then the corresponding DBG_VALUEs must sink.
MapVector<MachineInstr *, MIRegs::second_type> DbgValsToSinkMap;
- for (auto &MO : MI.operands()) {
- if (!MO.isReg() || !MO.isDef())
- continue;
-
+ for (auto &MO : MI.all_defs()) {
for (auto RI = MCRegUnitIterator(MO.getReg(), TRI); RI.isValid(); ++RI) {
for (const auto &MIRegs : SeenDbgInstrs.lookup(*RI)) {
auto &Regs = DbgValsToSinkMap[MIRegs.first];
diff --git a/llvm/lib/CodeGen/MachineUniformityAnalysis.cpp b/llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
index cc8cdaff9f0ed..b76ecdcae82ba 100644
--- a/llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
+++ b/llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
@@ -20,9 +20,7 @@ using namespace llvm;
template <>
bool llvm::GenericUniformityAnalysisImpl<MachineSSAContext>::hasDivergentDefs(
const MachineInstr &I) const {
- for (auto &op : I.operands()) {
- if (!op.isReg() || !op.isDef())
- continue;
+ for (auto &op : I.all_defs()) {
if (isDivergent(op.getReg()))
return true;
}
@@ -36,9 +34,7 @@ bool llvm::GenericUniformityAnalysisImpl<MachineSSAContext>::markDefsDivergent(
const auto &MRI = F.getRegInfo();
const auto &RBI = *F.getSubtarget().getRegBankInfo();
const auto &TRI = *MRI.getTargetRegisterInfo();
- for (auto &op : Instr.operands()) {
- if (!op.isReg() || !op.isDef())
- continue;
+ for (auto &op : Instr.all_defs()) {
if (!op.getReg().isVirtual())
continue;
assert(!op.getSubReg());
@@ -84,9 +80,7 @@ void llvm::GenericUniformityAnalysisImpl<MachineSSAContext>::pushUsers(
assert(!isAlwaysUniform(Instr));
if (Instr.isTerminator())
return;
- for (const MachineOperand &op : Instr.operands()) {
- if (!op.isReg() || !op.isDef())
- continue;
+ for (const MachineOperand &op : Instr.all_defs()) {
auto Reg = op.getReg();
if (isDivergent(Reg))
pushUsers(Reg);
@@ -119,9 +113,7 @@ void llvm::GenericUniformityAnalysisImpl<MachineSSAContext>::
propagateTemporalDivergence(const MachineInstr &I,
const MachineCycle &DefCycle) {
const auto &RegInfo = F.getRegInfo();
- for (auto &Op : I.operands()) {
- if (!Op.isReg() || !Op.isDef())
- continue;
+ for (auto &Op : I.all_defs()) {
if (!Op.getReg().isVirtual())
continue;
auto Reg = Op.getReg();
diff --git a/llvm/lib/CodeGen/ModuloSchedule.cpp b/llvm/lib/CodeGen/ModuloSchedule.cpp
index af9fef0720f9f..0bef513342ff1 100644
--- a/llvm/lib/CodeGen/ModuloSchedule.cpp
+++ b/llvm/lib/CodeGen/ModuloSchedule.cpp
@@ -74,10 +74,7 @@ void ModuloScheduleExpander::expand() {
// stage
diff erence for each use. Keep the maximum value.
for (MachineInstr *MI : Schedule.getInstructions()) {
int DefStage = Schedule.getStage(MI);
- for (const MachineOperand &Op : MI->operands()) {
- if (!Op.isReg() || !Op.isDef())
- continue;
-
+ for (const MachineOperand &Op : MI->all_defs()) {
Register Reg = Op.getReg();
unsigned MaxDiff = 0;
bool PhiIsSwapped = false;
@@ -743,9 +740,7 @@ void ModuloScheduleExpander::removeDeadInstructions(MachineBasicBlock *KernelBB,
continue;
}
bool used = true;
- for (const MachineOperand &MO : MI->operands()) {
- if (!MO.isReg() || !MO.isDef())
- continue;
+ for (const MachineOperand &MO : MI->all_defs()) {
Register reg = MO.getReg();
// Assume physical registers are used, unless they are marked dead.
if (reg.isPhysical()) {
diff --git a/llvm/lib/CodeGen/ProcessImplicitDefs.cpp b/llvm/lib/CodeGen/ProcessImplicitDefs.cpp
index 73ad11f1c2f8b..be81ecab9c897 100644
--- a/llvm/lib/CodeGen/ProcessImplicitDefs.cpp
+++ b/llvm/lib/CodeGen/ProcessImplicitDefs.cpp
@@ -72,8 +72,8 @@ bool ProcessImplicitDefs::canTurnIntoImplicitDef(MachineInstr *MI) {
!MI->isRegSequence() &&
!MI->isPHI())
return false;
- for (const MachineOperand &MO : MI->operands())
- if (MO.isReg() && MO.isUse() && MO.readsReg())
+ for (const MachineOperand &MO : MI->all_uses())
+ if (MO.readsReg())
return false;
return true;
}
diff --git a/llvm/lib/CodeGen/RDFGraph.cpp b/llvm/lib/CodeGen/RDFGraph.cpp
index dcb1a44c75e4a..a7440ce0301e2 100644
--- a/llvm/lib/CodeGen/RDFGraph.cpp
+++ b/llvm/lib/CodeGen/RDFGraph.cpp
@@ -1254,8 +1254,8 @@ void DataFlowGraph::buildStmt(NodeAddr<BlockNode*> BA, MachineInstr &In) {
auto isDefUndef = [this] (const MachineInstr &In, RegisterRef DR) -> bool {
// This instruction defines DR. Check if there is a use operand that
// would make DR live on entry to the instruction.
- for (const MachineOperand &Op : In.operands()) {
- if (!Op.isReg() || Op.getReg() == 0 || !Op.isUse() || Op.isUndef())
+ for (const MachineOperand &Op : In.all_uses()) {
+ if (Op.getReg() == 0 || Op.isUndef())
continue;
RegisterRef UR = makeRegRef(Op);
if (PRI.alias(DR, UR))
diff --git a/llvm/lib/CodeGen/RDFLiveness.cpp b/llvm/lib/CodeGen/RDFLiveness.cpp
index 0cd7364396606..9afa9e990f811 100644
--- a/llvm/lib/CodeGen/RDFLiveness.cpp
+++ b/llvm/lib/CodeGen/RDFLiveness.cpp
@@ -933,12 +933,12 @@ void Liveness::resetKills(MachineBasicBlock *B) {
continue;
MI.clearKillInfo();
- for (auto &Op : MI.operands()) {
+ for (auto &Op : MI.all_defs()) {
// An implicit def of a super-register may not necessarily start a
// live range of it, since an implicit use could be used to keep parts
// of it live. Instead of analyzing the implicit operands, ignore
// implicit defs.
- if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
+ if (Op.isImplicit())
continue;
Register R = Op.getReg();
if (!R.isPhysical())
@@ -946,8 +946,8 @@ void Liveness::resetKills(MachineBasicBlock *B) {
for (MCPhysReg SR : TRI.subregs_inclusive(R))
Live.reset(SR);
}
- for (auto &Op : MI.operands()) {
- if (!Op.isReg() || !Op.isUse() || Op.isUndef())
+ for (auto &Op : MI.all_uses()) {
+ if (Op.isUndef())
continue;
Register R = Op.getReg();
if (!R.isPhysical())
diff --git a/llvm/lib/CodeGen/RegAllocFast.cpp b/llvm/lib/CodeGen/RegAllocFast.cpp
index fe2746db62d7d..40d2e968f46f2 100644
--- a/llvm/lib/CodeGen/RegAllocFast.cpp
+++ b/llvm/lib/CodeGen/RegAllocFast.cpp
@@ -1450,9 +1450,7 @@ void RegAllocFast::allocateInstruction(MachineInstr &MI) {
// like ` = OP undef %X, %X` both operands need the same register assign
// so we should perform the normal assignment first.
if (HasUndefUse) {
- for (MachineOperand &MO : MI.uses()) {
- if (!MO.isReg() || !MO.isUse())
- continue;
+ for (MachineOperand &MO : MI.all_uses()) {
Register Reg = MO.getReg();
if (!Reg.isVirtual() || !shouldAllocateRegister(Reg))
continue;
@@ -1464,8 +1462,8 @@ void RegAllocFast::allocateInstruction(MachineInstr &MI) {
// Free early clobbers.
if (HasEarlyClobber) {
- for (MachineOperand &MO : llvm::reverse(MI.operands())) {
- if (!MO.isReg() || !MO.isDef() || !MO.isEarlyClobber())
+ for (MachineOperand &MO : llvm::reverse(MI.all_defs())) {
+ if (!MO.isEarlyClobber())
continue;
assert(!MO.getSubReg() && "should be already handled in def processing");
diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp
index c0c07bc817ac1..68827d0ea5e60 100644
--- a/llvm/lib/CodeGen/RegisterCoalescer.cpp
+++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp
@@ -1251,8 +1251,8 @@ bool RegisterCoalescer::removePartialRedundancy(const CoalescerPair &CP,
static bool definesFullReg(const MachineInstr &MI, Register Reg) {
assert(!Reg.isPhysical() && "This code cannot handle physreg aliasing");
- for (const MachineOperand &Op : MI.operands()) {
- if (!Op.isReg() || !Op.isDef() || Op.getReg() != Reg)
+ for (const MachineOperand &Op : MI.all_defs()) {
+ if (Op.getReg() != Reg)
continue;
// Return true if we define the full register or don't care about the value
// inside other subregisters.
@@ -1707,8 +1707,8 @@ MachineInstr *RegisterCoalescer::eliminateUndefCopy(MachineInstr *CopyMI) {
// is still part of the function (but about to be erased), mark all
// defs of DstReg in it as <undef>, so that shrinkToUses would
// ignore them.
- for (MachineOperand &MO : CopyMI->operands())
- if (MO.isReg() && MO.isDef() && MO.getReg() == DstReg)
+ for (MachineOperand &MO : CopyMI->all_defs())
+ if (MO.getReg() == DstReg)
MO.setIsUndef(true);
LIS->shrinkToUses(&DstLI);
@@ -2564,8 +2564,8 @@ class JoinVals {
LaneBitmask JoinVals::computeWriteLanes(const MachineInstr *DefMI, bool &Redef)
const {
LaneBitmask L;
- for (const MachineOperand &MO : DefMI->operands()) {
- if (!MO.isReg() || MO.getReg() != Reg || !MO.isDef())
+ for (const MachineOperand &MO : DefMI->all_defs()) {
+ if (MO.getReg() != Reg)
continue;
L |= TRI->getSubRegIndexLaneMask(
TRI->composeSubRegIndices(SubIdx, MO.getSubReg()));
@@ -3033,8 +3033,8 @@ bool JoinVals::usesLanes(const MachineInstr &MI, Register Reg, unsigned SubIdx,
LaneBitmask Lanes) const {
if (MI.isDebugOrPseudoInstr())
return false;
- for (const MachineOperand &MO : MI.operands()) {
- if (!MO.isReg() || MO.isDef() || MO.getReg() != Reg)
+ for (const MachineOperand &MO : MI.all_uses()) {
+ if (MO.getReg() != Reg)
continue;
if (!MO.readsReg())
continue;
diff --git a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
index 57fd31879b383..239b44857c288 100644
--- a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
+++ b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -208,8 +208,7 @@ void ScheduleDAGInstrs::addSchedBarrierDeps() {
ExitSU.setInstr(ExitMI);
// Add dependencies on the defs and uses of the instruction.
if (ExitMI) {
- for (const MachineOperand &MO : ExitMI->operands()) {
- if (!MO.isReg() || MO.isDef()) continue;
+ for (const MachineOperand &MO : ExitMI->all_uses()) {
Register Reg = MO.getReg();
if (Reg.isPhysical()) {
Uses.insert(PhysRegSUOper(&ExitSU, -1, Reg));
diff --git a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
index f57ad337dc651..7faf5f52249e3 100644
--- a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -1565,8 +1565,8 @@ TwoAddressInstructionPass::processTiedPairs(MachineInstr *MI,
if (AllUsesCopied) {
LaneBitmask RemainingUses = LaneBitmask::getNone();
// Replace other (un-tied) uses of regB with LastCopiedReg.
- for (MachineOperand &MO : MI->operands()) {
- if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) {
+ for (MachineOperand &MO : MI->all_uses()) {
+ if (MO.getReg() == RegB) {
if (MO.getSubReg() == SubRegB && !IsEarlyClobber) {
if (MO.isKill()) {
MO.setIsKill(false);
@@ -1618,8 +1618,8 @@ TwoAddressInstructionPass::processTiedPairs(MachineInstr *MI,
// regB is still used in this instruction, but a kill flag was
// removed from a
diff erent tied use of regB, so now we need to add
// a kill flag to one of the remaining uses of regB.
- for (MachineOperand &MO : MI->operands()) {
- if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) {
+ for (MachineOperand &MO : MI->all_uses()) {
+ if (MO.getReg() == RegB) {
MO.setIsKill(true);
break;
}
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