[lld] 2b4c13f - [ARM] Emit code alignment after .arm and .thumb directives
Fangrui Song via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 1 11:05:44 PDT 2023
Author: Antonio Abbatangelo
Date: 2023-06-01T11:05:38-07:00
New Revision: 2b4c13f757478d8dc705ebec9598a3cd154dadcc
URL: https://github.com/llvm/llvm-project/commit/2b4c13f757478d8dc705ebec9598a3cd154dadcc
DIFF: https://github.com/llvm/llvm-project/commit/2b4c13f757478d8dc705ebec9598a3cd154dadcc.diff
LOG: [ARM] Emit code alignment after .arm and .thumb directives
Emit a 4-byte alignment after the .arm directive and a 2-byte alignment
after the .thumb directive. The new behavior matches GNU assembler.
Fixes #53386
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D147763
Added:
llvm/test/MC/ARM/directive-arm-thumb-alignment.s
Modified:
lld/test/ELF/arm-bl-v4t.s
lld/test/ELF/arm-bl-v6-inrange.s
lld/test/ELF/arm-fix-cortex-a8-nopatch.s
lld/test/ELF/arm-fix-cortex-a8-recognize.s
lld/test/ELF/arm-thunk-multipass.s
llvm/docs/ReleaseNotes.rst
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
llvm/test/MC/ARM/directive-arch-mode-switch.s
llvm/test/MC/ARM/misaligned-blx.s
llvm/test/MC/ARM/thumb-function-address.s
llvm/test/MC/ARM/thumb-types.s
Removed:
################################################################################
diff --git a/lld/test/ELF/arm-bl-v4t.s b/lld/test/ELF/arm-bl-v4t.s
index bf423b965e913..aa9f1632ec509 100644
--- a/lld/test/ELF/arm-bl-v4t.s
+++ b/lld/test/ELF/arm-bl-v4t.s
@@ -154,11 +154,11 @@ thumb_start:
// FAR-EB-PIE-NEXT: 100002c: 04 ff ff d9 .word 0x04ffffd9
// NEAR-LABEL: <_start>:
-// NEAR-NEXT: 1000000: bl 0x100000c <thumb_start+0x4> @ imm = #4
+// NEAR-NEXT: 1000000: bl 0x1000010 <target> @ imm = #8
// NEAR-NEXT: bx lr
// NEAR-EMPTY:
// NEAR-LABEL: <thumb_start>:
-// NEAR-NEXT: 1000008: bl 0x1000012 <thumb_target> @ imm = #6
+// NEAR-NEXT: 1000008: bl 0x1000014 <thumb_target> @ imm = #8
// NEAR-NEXT: bx lr
.section .high, "ax", %progbits
@@ -187,10 +187,10 @@ thumb_target:
// FAR-PIE-NEXT: 6000004: bx lr
// NEAR-LABEL: <target>:
-// NEAR-LABEL: 100000e: bx lr
+// NEAR-LABEL: 1000010: bx lr
// NEAR-EMPTY:
// NEAR-NEXT: <thumb_target>:
-// NEAR-NEXT: 1000012: bx lr
+// NEAR-NEXT: 1000014: bx lr
#--- far.lds
diff --git a/lld/test/ELF/arm-bl-v6-inrange.s b/lld/test/ELF/arm-bl-v6-inrange.s
index 24e10b5d1bafe..1a298cc45928b 100644
--- a/lld/test/ELF/arm-bl-v6-inrange.s
+++ b/lld/test/ELF/arm-bl-v6-inrange.s
@@ -38,8 +38,8 @@ thumbfunc:
// CHECK-NEXT: 500004: f3ff effe blx 0x900004 <armfunc>
// CHECK-NEXT: 500008: 4770 bx lr
- .arm
.section .callee_high, "ax", %progbits
+ .arm
.globl armfunc
.type armfunc, %function
armfunc:
diff --git a/lld/test/ELF/arm-fix-cortex-a8-nopatch.s b/lld/test/ELF/arm-fix-cortex-a8-nopatch.s
index 0dad04779f0ed..5b029e46782ce 100644
--- a/lld/test/ELF/arm-fix-cortex-a8-nopatch.s
+++ b/lld/test/ELF/arm-fix-cortex-a8-nopatch.s
@@ -75,7 +75,7 @@ target4:
// CALLSITE4: 00025002 <target4>:
// CALLSITE4-NEXT: 25002: nop.w
- .space 4084
+ .space 4082
.type target5, %function
target5:
@@ -83,14 +83,15 @@ target5:
/// a 32-bit thumb instruction, but in ARM state (illegal instruction), we
/// should not decode and match it as Thumb, expect no patch.
.arm
- .inst 0x800f3af /// nop.w encoding in Thumb
+ .short 0xbf00 // nop encoding in Thumb for alignment
+ .inst 0xf3af8000 /// nop.w encoding in Thumb
.thumb
.thumb_func
source5:
beq.w target5
// CALLSITE5: 00025ffe <source5>:
-// CALLSITE5-NEXT: 25ffe: beq.w 0x25ffa <target5>
+// CALLSITE5-NEXT: 25ffe: beq.w 0x25ff8 <target5>
/// Edge case where two word sequence starts at offset 0xffc, check that
/// we don't match. In this case the branch will be completely in the 2nd
diff --git a/lld/test/ELF/arm-fix-cortex-a8-recognize.s b/lld/test/ELF/arm-fix-cortex-a8-recognize.s
index 21839448ff567..ab0ceb8c76cc2 100644
--- a/lld/test/ELF/arm-fix-cortex-a8-recognize.s
+++ b/lld/test/ELF/arm-fix-cortex-a8-recognize.s
@@ -26,7 +26,7 @@
// CHECK-RELOCATABLE-LLD-NOT: ld.lld: detected cortex-a8-657419 erratum sequence
/// Basic tests for the -fix-cortex-a8 erratum fix. The full details of the
-/// erratum and the patch are in ARMA8ErrataFix.cpp . The test creates an
+/// erratum and the patch are in ARMErrataFix.cpp . The test creates an
/// instance of the erratum every 4KiB (32-bit non-branch, followed by 32-bit
/// branch instruction, where the branch instruction spans two 4 KiB regions,
/// and the branch destination is in the first 4KiB region.
@@ -163,7 +163,7 @@ target7:
// CALLSITE7-NEXT: 27ffe: bne.w 0x2901c <__CortexA8657417_27FFE>
.section .text.6, "ax", %progbits
- .space 4082
+ .space 4080
.arm
.global target8
.type target8, %function
diff --git a/lld/test/ELF/arm-thunk-multipass.s b/lld/test/ELF/arm-thunk-multipass.s
index c9232c3df986f..210d9634624bc 100644
--- a/lld/test/ELF/arm-thunk-multipass.s
+++ b/lld/test/ELF/arm-thunk-multipass.s
@@ -4,7 +4,7 @@
// The output file is large, most of it zeroes. We dissassemble only the
// parts we need to speed up the test and avoid a large output file
// RUN: llvm-objdump --no-print-imm-hex -d %t2 --start-address=0x100002 --stop-address=0x10000a | FileCheck --check-prefix=CHECK1 %s
-// RUN: llvm-objdump --no-print-imm-hex -d %t2 --start-address=0x1000008 --stop-address=0x1000026 | FileCheck --check-prefix=CHECK2 %s
+// RUN: llvm-objdump --no-print-imm-hex -d %t2 --start-address=0x1000004 --stop-address=0x1000026 | FileCheck --check-prefix=CHECK2 %s
// RUN: llvm-objdump --no-print-imm-hex -d %t2 --start-address=0x1100014 --stop-address=0x1100022 | FileCheck --check-prefix=CHECK3 %s
// In this test case a branch that is in range and does not need its range
// extended can be pushed out of range by another Thunk, necessitating another
@@ -59,8 +59,9 @@ target2:
.type arm_target, %function
arm_target:
bx lr
+// CHECK2: 01000004 <arm_target>:
// CHECK2: <__Thumbv7ABSLongThunk_arm_target>:
-// CHECK2-NEXT: 1000008: f240 0c02 movw r12, #2
+// CHECK2-NEXT: 1000008: f240 0c04 movw r12, #4
// CHECK2-NEXT: 100000c: f2c0 1c00 movt r12, #256
// CHECK2-NEXT: 1000010: 4760 bx r12
// CHECK2: <__Thumbv7ABSLongThunk_target>:
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index a3c9d93ac65c0..5008821a2f465 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -107,6 +107,9 @@ Changes to the ARM Backend
have integer MVE instructions (and therefore have FP registers) but
no scalar or vector floating point computation.
+- The ``.arm`` directive now aligns code to the next 4-byte boundary, and
+ the ``.thumb`` directive aligns code to the next 2-byte boundary.
+
Changes to the AVR Backend
--------------------------
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 95fb27f9f63dd..4007161ce3a95 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -11418,6 +11418,7 @@ bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
SwitchMode();
getParser().getStreamer().emitAssemblerFlag(MCAF_Code16);
+ getParser().getStreamer().emitCodeAlignment(Align(2), &getSTI(), 0);
return false;
}
@@ -11430,6 +11431,7 @@ bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
if (isThumb())
SwitchMode();
getParser().getStreamer().emitAssemblerFlag(MCAF_Code32);
+ getParser().getStreamer().emitCodeAlignment(Align(4), &getSTI(), 0);
return false;
}
diff --git a/llvm/test/MC/ARM/directive-arch-mode-switch.s b/llvm/test/MC/ARM/directive-arch-mode-switch.s
index abb88a60163f1..2e5473844930e 100644
--- a/llvm/test/MC/ARM/directive-arch-mode-switch.s
+++ b/llvm/test/MC/ARM/directive-arch-mode-switch.s
@@ -35,6 +35,7 @@
@ Switch to ARM mode
.arm
@ CHECK: .code 32
+@ CHECK: .p2align 2
@ In ARM mode, switch to a CPU which has ARM and Thumb, no warning or .code directive (stay in ARM mode)
.cpu cortex-a8
diff --git a/llvm/test/MC/ARM/directive-arm-thumb-alignment.s b/llvm/test/MC/ARM/directive-arm-thumb-alignment.s
new file mode 100644
index 0000000000000..b90c76d2b121c
--- /dev/null
+++ b/llvm/test/MC/ARM/directive-arm-thumb-alignment.s
@@ -0,0 +1,63 @@
+@ RUN: llvm-mc -triple armv7-elf -filetype obj -o - %s | llvm-readelf -S -s - | FileCheck %s
+
+@ CHECK: [Nr] Name Type Address Off Size ES Flg Lk Inf Al
+@ CHECK-NEXT: [ 0] NULL 00000000 000000 000000 00 0 0 0
+@ CHECK-NEXT: [ 1] .strtab STRTAB 00000000 {{.*}} {{.*}} 00 0 0 1
+@ CHECK-NEXT: [ 2] .text PROGBITS 00000000 {{.*}} 00000d 00 AX 0 0 4
+@ CHECK-NEXT: [ 3] .arm_aligned PROGBITS 00000000 {{.*}} 000005 00 AX 0 0 4
+@ CHECK-NEXT: [ 4] .thumb_aligned PROGBITS 00000000 {{.*}} 000002 00 AX 0 0 2
+
+@ CHECK: Num: Value Size Type Bind Vis Ndx Name
+@ CHECK-NEXT: 0: 00000000 0 NOTYPE LOCAL DEFAULT UND
+@ CHECK-NEXT: 1: 00000001 0 FUNC LOCAL DEFAULT 2 aligned_thumb
+@ CHECK-NEXT: 2: 00000000 0 NOTYPE LOCAL DEFAULT 2 $t.0
+@ CHECK-NEXT: 3: 00000004 0 FUNC LOCAL DEFAULT 2 thumb_to_arm
+@ CHECK-NEXT: 4: 00000004 0 NOTYPE LOCAL DEFAULT 2 $a.1
+@ CHECK-NEXT: 5: 00000008 0 NOTYPE LOCAL DEFAULT 2 $d.2
+@ CHECK-NEXT: 6: 0000000b 0 FUNC LOCAL DEFAULT 2 unaligned_arm_to_thumb
+@ CHECK-NEXT: 7: 0000000a 0 NOTYPE LOCAL DEFAULT 2 $t.3
+
+.thumb
+
+.type aligned_thumb,%function
+aligned_thumb:
+ nop
+
+@ Above function has size 2 (at offset 0)
+@ Expect alignment of +2 (to offset 4)
+.arm
+
+.type thumb_to_arm,%function
+thumb_to_arm:
+ nop
+
+.byte 0
+
+@ Above function has size 5 (at offset 4)
+@ Expect alignment of +1 (to offset 10)
+.thumb
+.type unaligned_arm_to_thumb,%function
+unaligned_arm_to_thumb:
+ nop
+
+.byte 0
+
+@ Above section has size 13 (at offset 34)
+@ Expect alignment of +3 (to offset 44)
+.section .arm_aligned, "ax"
+.arm
+
+.type arm_aligned_section,%function
+arm_aligned_section:
+ nop
+
+.byte 0
+
+@ Above section has size 5 (at offset 44)
+@ Expect alignment of +1 (to offset 4a)
+.section .thumb_aligned, "ax"
+.thumb
+
+.type thumb_aligned_section,%function
+thumb_aligned_section:
+ nop
diff --git a/llvm/test/MC/ARM/misaligned-blx.s b/llvm/test/MC/ARM/misaligned-blx.s
index f9250bf535ba6..0a178d8c625ec 100644
--- a/llvm/test/MC/ARM/misaligned-blx.s
+++ b/llvm/test/MC/ARM/misaligned-blx.s
@@ -8,6 +8,7 @@ _f1:
@ A misaligned ARM destination.
.arm
+ .byte 0x0
.globl _misaligned
_misaligned:
bx lr
diff --git a/llvm/test/MC/ARM/thumb-function-address.s b/llvm/test/MC/ARM/thumb-function-address.s
index 9200b54a80e98..753a049137bbf 100644
--- a/llvm/test/MC/ARM/thumb-function-address.s
+++ b/llvm/test/MC/ARM/thumb-function-address.s
@@ -39,4 +39,4 @@ label:
@ CHECK-NEXT: 00000003 0 FUNC LOCAL DEFAULT 2 foo_resolver
@ CHECK-NEXT: 00000003 0 IFUNC LOCAL DEFAULT 2 foo
@ CHECK-NEXT: 00000004 0 FUNC LOCAL DEFAULT 2 label
-@ CHECK-NEXT: 00000006 0 NOTYPE LOCAL DEFAULT 2 $a.1
+@ CHECK-NEXT: 00000008 0 NOTYPE LOCAL DEFAULT 2 $a.1
diff --git a/llvm/test/MC/ARM/thumb-types.s b/llvm/test/MC/ARM/thumb-types.s
index 265f23ea6c427..cb1b47e1fa7fb 100644
--- a/llvm/test/MC/ARM/thumb-types.s
+++ b/llvm/test/MC/ARM/thumb-types.s
@@ -6,15 +6,15 @@
@ CHECK-NEXT: 2: 00000000 0 NOTYPE LOCAL DEFAULT 2 $t.0
@ CHECK-NEXT: 3: 00000002 0 OBJECT LOCAL DEFAULT 2 implicit_data
@ CHECK-NEXT: 4: 00000002 0 NOTYPE LOCAL DEFAULT 2 $d.1
-@ CHECK-NEXT: 5: 00000006 0 FUNC LOCAL DEFAULT 2 arm_function
-@ CHECK-NEXT: 6: 00000006 0 NOTYPE LOCAL DEFAULT 2 $a.2
-@ CHECK-NEXT: 7: 0000000a 0 NOTYPE LOCAL DEFAULT 2 untyped_text_label
-@ CHECK-NEXT: 8: 0000000a 0 NOTYPE LOCAL DEFAULT 2 $t.3
-@ CHECK-NEXT: 9: 0000000d 0 FUNC LOCAL DEFAULT 2 explicit_function
-@ CHECK-NEXT: 10: 0000000e 0 NOTYPE LOCAL DEFAULT 2 $d.4
+@ CHECK-NEXT: 5: 00000008 0 FUNC LOCAL DEFAULT 2 arm_function
+@ CHECK-NEXT: 6: 00000008 0 NOTYPE LOCAL DEFAULT 2 $a.2
+@ CHECK-NEXT: 7: 0000000c 0 NOTYPE LOCAL DEFAULT 2 untyped_text_label
+@ CHECK-NEXT: 8: 0000000c 0 NOTYPE LOCAL DEFAULT 2 $t.3
+@ CHECK-NEXT: 9: 0000000f 0 FUNC LOCAL DEFAULT 2 explicit_function
+@ CHECK-NEXT: 10: 00000010 0 NOTYPE LOCAL DEFAULT 2 $d.4
@ CHECK-NEXT: 11: 00000000 4 TLS LOCAL DEFAULT 5 tls
-@ CHECK-NEXT: 12: 00000013 0 IFUNC LOCAL DEFAULT 2 indirect_function
-@ CHECK-NEXT: 13: 00000012 0 NOTYPE LOCAL DEFAULT 2 $t.5
+@ CHECK-NEXT: 12: 00000015 0 IFUNC LOCAL DEFAULT 2 indirect_function
+@ CHECK-NEXT: 13: 00000014 0 NOTYPE LOCAL DEFAULT 2 $t.5
@ CHECK-NEXT: 14: 00000000 0 NOTYPE LOCAL DEFAULT 4 untyped_data_label
@ CHECK-NEXT: 15: 00000000 0 NOTYPE LOCAL DEFAULT 4 $t.6
@ CHECK-NEXT: 16: 00000002 0 OBJECT LOCAL DEFAULT 4 explicit_data
More information about the llvm-commits
mailing list