[PATCH] D151905: add s17

[Thorsten via Phabricator via llvm-commits]

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ran into legalization issues with larger non-power-of-2


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D151905

Files:
  llvm/test/CodeGen/X86/GlobalISel/legalize-bswap.mir


Index: llvm/test/CodeGen/X86/GlobalISel/legalize-bswap.mir
===================================================================
--- llvm/test/CodeGen/X86/GlobalISel/legalize-bswap.mir
+++ llvm/test/CodeGen/X86/GlobalISel/legalize-bswap.mir
@@ -2,7 +2,35 @@
 # RUN: llc -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=X86-64
 # RUN: llc -mtriple=i386-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=X86-32
 
-# test BSWAP s32 and s64
+# test BSWAP s16, s32, and s64
+
+...
+---
+name:            test_bswaps17
+body:             |
+  bb.1:
+    ; X86-64-LABEL: name: test_bswaps17
+    ; X86-64: [[DEF:%[0-9]+]]:_(s17) = IMPLICIT_DEF
+    ; X86-64-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[DEF]](s17)
+    ; X86-64-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[ANYEXT]]
+    ; X86-64-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 15
+    ; X86-64-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BSWAP]], [[C]](s8)
+    ; X86-64-NEXT: [[TRUNC:%[0-9]+]]:_(s17) = G_TRUNC [[LSHR]](s32)
+    ; X86-64-NEXT: [[COPY:%[0-9]+]]:_(s17) = COPY [[TRUNC]](s17)
+    ; X86-64-NEXT: RET 0, implicit [[COPY]](s17)
+    ; X86-32-LABEL: name: test_bswaps17
+    ; X86-32: [[DEF:%[0-9]+]]:_(s17) = IMPLICIT_DEF
+    ; X86-32-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[DEF]](s17)
+    ; X86-32-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[ANYEXT]]
+    ; X86-32-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 15
+    ; X86-32-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BSWAP]], [[C]](s8)
+    ; X86-32-NEXT: [[TRUNC:%[0-9]+]]:_(s17) = G_TRUNC [[LSHR]](s32)
+    ; X86-32-NEXT: [[COPY:%[0-9]+]]:_(s17) = COPY [[TRUNC]](s17)
+    ; X86-32-NEXT: RET 0, implicit [[COPY]](s17)
+    %0:_(s17) = IMPLICIT_DEF
+    %1:_(s17) = G_BSWAP %0
+    %2:_(s17) = COPY %1(s17)
+    RET 0, implicit %2
 
 ...
 ---


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