[PATCH] D99750: [LV, VP] RFC: VP intrinsics support for the Loop Vectorizer (Proof-of-Concept)

[Alexey Bataev via Phabricator via llvm-commits]

ABataev updated this revision to Diff 527481.
ABataev added a comment.

1. Rebase
2. Address comments (added a test for UserIF)
3. As agreeed on the RISC-V meeting, left only emission of loads/stores.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99750/new/

https://reviews.llvm.org/D99750

Files:
  llvm/include/llvm/IR/IRBuilder.h
  llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
  llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
  llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
  llvm/lib/Transforms/Vectorize/VPlan.h
  llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
  llvm/lib/Transforms/Vectorize/VPlanValue.h
  llvm/test/Transforms/LoopVectorize/RISCV/vectorize-vp-intrinsics.ll
  llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics.ll
  llvm/test/Transforms/LoopVectorize/X86/vectorize-vp-intrinsics.ll
  llvm/test/Transforms/LoopVectorize/X86/vplan-vp-intrinsics.ll

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