[PATCH] D151898: [RISCV] Guard Advance Interrupt Architecture CSRs with Smaia and Ssaia extensions.

[garvit gupta via Phabricator via llvm-commits]

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Smaia and Ssaia extension for advance interrupt architecture CSRs are added in
this patch - https://reviews.llvm.org/D148066. However, the CSRs were not being
guarded by these extensions.

This patch adds the same because these CSRs should be recognized by name when
assembling/disassembling if their corresponding extensions are enabled.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D151898

Files:
  llvm/lib/Target/RISCV/RISCVSystemOperands.td
  llvm/test/MC/RISCV/hypervisor-csr-names.s
  llvm/test/MC/RISCV/machine-csr-names.s
  llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
  llvm/test/MC/RISCV/rv32-machine-csr-names.s
  llvm/test/MC/RISCV/rv32-supervisor-csr-names.s
  llvm/test/MC/RISCV/rvi-aliases-valid.s
  llvm/test/MC/RISCV/supervisor-csr-names.s

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