[PATCH] D151177: [RISCV] Add i32 as a legal type for GPR register class.

[Craig Topper via Phabricator via llvm-commits]

craig.topper updated this revision to Diff 527301.
craig.topper added a comment.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151177/new/

https://reviews.llvm.org/D151177

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoA.td
  llvm/lib/Target/RISCV/RISCVInstrInfoD.td
  llvm/lib/Target/RISCV/RISCVInstrInfoF.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
  llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
  llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZicond.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZk.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td

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