[llvm] 78a2240 - [RISCV][NFC] Add isF argument to SchedSEWSet

via llvm-commits llvm-commits at lists.llvm.org
Wed May 31 21:48:17 PDT 2023


Author: wangpc
Date: 2023-06-01T12:44:49+08:00
New Revision: 78a22401728f2fa502d52676fa52263da2446395

URL: https://github.com/llvm/llvm-project/commit/78a22401728f2fa502d52676fa52263da2446395
DIFF: https://github.com/llvm/llvm-project/commit/78a22401728f2fa502d52676fa52263da2446395.diff

LOG: [RISCV][NFC] Add isF argument to SchedSEWSet

So that we can remove `SchedSEWSetF` and simplify some code.

Reviewed By: michaelmaitland

Differential Revision: https://reviews.llvm.org/D151790

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
    llvm/lib/Target/RISCV/RISCVScheduleV.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index d0d462287726..30672f66b55f 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -2364,7 +2364,7 @@ multiclass VPseudoVCLS_V {
 multiclass VPseudoVSQR_V {
   foreach m = MxListF in {
     defvar mx = m.MX;
-    defvar sews = SchedSEWSetF<m.MX>.val;
+    defvar sews = SchedSEWSet<m.MX, /*isF*/ 1>.val;
 
     let VLMul = m.value in
       foreach e = sews in {
@@ -2719,7 +2719,7 @@ multiclass VPseudoVFMUL_VV_VF {
 multiclass VPseudoVFDIV_VV_VF {
   foreach m = MxListF in {
     defvar mx = m.MX;
-    defvar sews = SchedSEWSetF<mx>.val;
+    defvar sews = SchedSEWSet<mx, /*isF*/ 1>.val;
     foreach e = sews in {
       defvar WriteVFDivV_MX_E = !cast<SchedWrite>("WriteVFDivV_" # mx # "_E" # e);
       defvar ReadVFDivV_MX_E = !cast<SchedRead>("ReadVFDivV_" # mx # "_E" # e);
@@ -2732,7 +2732,7 @@ multiclass VPseudoVFDIV_VV_VF {
   foreach f = FPList in {
     foreach m = f.MxList in {
       defvar mx = m.MX;
-      defvar sews = SchedSEWSetF<mx>.val;
+      defvar sews = SchedSEWSet<mx, /*isF*/ 1>.val;
       foreach e = sews in {
         defvar WriteVFDivF_MX_E = !cast<SchedWrite>("WriteVFDivF_" # mx # "_E" # e);
         defvar ReadVFDivV_MX_E = !cast<SchedRead>("ReadVFDivV_" # mx # "_E" # e);
@@ -2749,7 +2749,7 @@ multiclass VPseudoVFRDIV_VF {
   foreach f = FPList in {
     foreach m = f.MxList in {
       defvar mx = m.MX;
-      defvar sews = SchedSEWSetF<mx>.val;
+      defvar sews = SchedSEWSet<mx, /*isF*/ 1>.val;
       foreach e = sews in {
         defvar WriteVFDivF_MX_E = !cast<SchedWrite>("WriteVFDivF_" # mx # "_E" # e);
         defvar ReadVFDivV_MX_E = !cast<SchedRead>("ReadVFDivV_" # mx # "_E" # e);
@@ -3464,7 +3464,7 @@ multiclass VPseudoVRED_VS {
 multiclass VPseudoVWRED_VS {
   foreach m = MxListWRed in {
     defvar mx = m.MX;
-    foreach e = SchedSEWSet<mx, 1>.val in {
+    foreach e = SchedSEWSet<mx, /*isF*/ 0, /*isWidening*/ 1>.val in {
       defvar WriteVIWRedV_From_MX_E = !cast<SchedWrite>("WriteVIWRedV_From_" # mx # "_E" # e);
       defm _VS : VPseudoTernaryWithTailPolicy_E<V_M1.vrclass, m.vrclass, V_M1.vrclass, m, e>,
                  Sched<[WriteVIWRedV_From_MX_E, ReadVIWRedV, ReadVIWRedV,
@@ -3476,7 +3476,7 @@ multiclass VPseudoVWRED_VS {
 multiclass VPseudoVFRED_VS {
   foreach m = MxListF in {
     defvar mx = m.MX;
-    foreach e = SchedSEWSetF<mx>.val in {
+    foreach e = SchedSEWSet<mx, /*isF*/ 1>.val in {
       defvar WriteVFRedV_From_MX_E = !cast<SchedWrite>("WriteVFRedV_From_" # mx # "_E" # e);
       defm _VS : VPseudoTernaryWithTailPolicy_E<V_M1.vrclass, m.vrclass, V_M1.vrclass, m, e>,
                  Sched<[WriteVFRedV_From_MX_E, ReadVFRedV, ReadVFRedV, ReadVFRedV,
@@ -3488,7 +3488,7 @@ multiclass VPseudoVFRED_VS {
 multiclass VPseudoVFREDO_VS {
   foreach m = MxListF in {
     defvar mx = m.MX;
-    foreach e = SchedSEWSetF<mx>.val in {
+    foreach e = SchedSEWSet<mx, /*isF*/ 1>.val in {
       defvar WriteVFRedOV_From_MX_E = !cast<SchedWrite>("WriteVFRedOV_From_" # mx # "_E" # e);
       defm _VS : VPseudoTernaryWithTailPolicy_E<V_M1.vrclass, m.vrclass, V_M1.vrclass, m, e>,
                  Sched<[WriteVFRedOV_From_MX_E, ReadVFRedOV, ReadVFRedOV,
@@ -3500,7 +3500,7 @@ multiclass VPseudoVFREDO_VS {
 multiclass VPseudoVFWRED_VS {
   foreach m = MxListFWRed in {
     defvar mx = m.MX;
-    foreach e = SchedSEWSetF<mx, 1>.val in {
+    foreach e = SchedSEWSet<mx, /*isF*/ 1, /*isWidening*/ 1>.val in {
       defvar WriteVFWRedV_From_MX_E = !cast<SchedWrite>("WriteVFWRedV_From_" # mx # "_E" # e);
       defm _VS : VPseudoTernaryWithTailPolicy_E<V_M1.vrclass, m.vrclass, V_M1.vrclass, m, e>,
                  Sched<[WriteVFWRedV_From_MX_E, ReadVFWRedV, ReadVFWRedV,

diff  --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
index 345dd90157e2..ef0159b94321 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -567,7 +567,7 @@ foreach mx = SchedMxList in {
   }
 }
 foreach mx = SchedMxListF in {
-  foreach sew = SchedSEWSetF<mx>.val in {
+  foreach sew = SchedSEWSet<mx, /*isF*/ 1>.val in {
     defvar Cycles = !mul(SiFive7GetDivOrSqrtFactor<sew>.c,
                          !div(SiFive7GetCyclesOnePerElement<mx, sew>.c, 4));
     defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;

diff  --git a/llvm/lib/Target/RISCV/RISCVScheduleV.td b/llvm/lib/Target/RISCV/RISCVScheduleV.td
index 5863f170d5d9..dd02c7f21d3a 100644
--- a/llvm/lib/Target/RISCV/RISCVScheduleV.td
+++ b/llvm/lib/Target/RISCV/RISCVScheduleV.td
@@ -20,8 +20,8 @@ defvar SchedMxListF = !listremove(SchedMxList, ["MF8"]);
 // Used for widening floating-point Reduction as it doesn't contain MF8.
 defvar SchedMxListFWRed = SchedMxListF;
 
-// For widening instructions, SEW will not be 64.
-class SchedSEWSet<string mx, bit isWidening = 0> {
+class SchedSEWSet<string mx, bit isF = 0, bit isWidening = 0> {
+  assert !or(!not(isF), !ne(mx, "MF8")), "LMUL shouldn't be MF8 for floating-point";
   defvar t = !cond(!eq(mx, "M1"):  [8, 16, 32, 64],
                    !eq(mx, "M2"):  [8, 16, 32, 64],
                    !eq(mx, "M4"):  [8, 16, 32, 64],
@@ -29,18 +29,11 @@ class SchedSEWSet<string mx, bit isWidening = 0> {
                    !eq(mx, "MF2"): [8, 16, 32],
                    !eq(mx, "MF4"): [8, 16],
                    !eq(mx, "MF8"): [8]);
-  list<int> val = !if(isWidening, !listremove(t, [64]), t);
-}
-
-// For floating-point instructions, SEW won't be 8.
-class SchedSEWSetF<string mx, bit isWidening = 0> {
-  defvar t = !cond(!eq(mx, "M1"):  [16, 32, 64],
-                   !eq(mx, "M2"):  [16, 32, 64],
-                   !eq(mx, "M4"):  [16, 32, 64],
-                   !eq(mx, "M8"):  [16, 32, 64],
-                   !eq(mx, "MF2"): [16, 32],
-                   !eq(mx, "MF4"): [16]);
-  list<int> val = !if(isWidening, !listremove(t, [64]), t);
+  // For floating-point instructions, SEW won't be 8.
+  defvar remove8 = !if(isF, !listremove(t, [8]), t);
+  // For widening instructions, SEW will not be 64.
+  defvar remove64 = !if(isWidening, !listremove(remove8, [64]), remove8);
+  list<int> val = remove64;
 }
 
 // Helper function to get the largest LMUL from MxList
@@ -52,7 +45,7 @@ class LargestLMUL<list<string> MxList> {
 // Helper function to get the smallest SEW that can be used with LMUL mx
 // Precondition: MxList is sorted in ascending LMUL order and SchedSEWSet<mx>
 class SmallestSEW<string mx, bit isF = 0> {
-  int r = !head(!if(isF, SchedSEWSetF<mx>.val, SchedSEWSet<mx>.val));
+  int r = !head(SchedSEWSet<mx, isF>.val);
 }
 
 // Creates WriteRes for (name, mx, resources) tuple
@@ -111,8 +104,7 @@ multiclass LMULSEWSchedWritesImpl<string name, list<string> MxList, bit isF = 0,
                                   bit isWidening = 0> {
   def name # "_WorstCase" : SchedWrite;
   foreach mx = MxList in {
-    foreach sew = !if(isF, SchedSEWSetF<mx, isWidening>.val,
-                      SchedSEWSet<mx, isWidening>.val) in
+    foreach sew = SchedSEWSet<mx, isF, isWidening>.val in
       def name # "_" # mx # "_E" # sew : SchedWrite;
   }
 }
@@ -120,8 +112,7 @@ multiclass LMULSEWSchedReadsImpl<string name, list<string> MxList, bit isF = 0,
                                  bit isWidening = 0> {
   def name # "_WorstCase" : SchedRead;
   foreach mx = MxList in {
-    foreach sew = !if(isF,SchedSEWSetF<mx, isWidening>.val,
-                      SchedSEWSet<mx, isWidening>.val) in
+    foreach sew = SchedSEWSet<mx, isF, isWidening>.val in
       def name # "_" # mx # "_E" # sew : SchedRead;
   }
 }
@@ -131,8 +122,7 @@ multiclass LMULSEWWriteResImpl<string name, list<ProcResourceKind> resources,
   if !exists<SchedWrite>(name # "_WorstCase") then
     def : WriteRes<!cast<SchedWrite>(name # "_WorstCase"), resources>;
   foreach mx = MxList in {
-    foreach sew = !if(isF,SchedSEWSetF<mx, isWidening>.val,
-                      SchedSEWSet<mx, isWidening>.val) in
+    foreach sew = SchedSEWSet<mx, isF, isWidening>.val in
       if !exists<SchedWrite>(name # "_" # mx # "_E" # sew) then
         def : WriteRes<!cast<SchedWrite>(name # "_" # mx # "_E" # sew), resources>;
   }
@@ -143,8 +133,7 @@ multiclass LMULSEWReadAdvanceImpl<string name, int val, list<SchedWrite> writes
   if !exists<SchedRead>(name # "_WorstCase") then
     def : ReadAdvance<!cast<SchedRead>(name # "_WorstCase"), val, writes>;
   foreach mx = MxList in {
-    foreach sew = !if(isF,SchedSEWSetF<mx, isWidening>.val,
-                      SchedSEWSet<mx, isWidening>.val) in
+    foreach sew = SchedSEWSet<mx, isF, isWidening>.val in
       if !exists<SchedRead>(name # "_" # mx # "_E" # sew) then
         def : ReadAdvance<!cast<SchedRead>(name # "_" # mx # "_E" # sew), val, writes>;
   }


        


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