[PATCH] D151482: [LV] Add support for minimum/maximum intrinsics

[Serguei Katkov via Phabricator via llvm-commits]

skatkov added a comment.

In D151482#4385109 <https://reviews.llvm.org/D151482#4385109>, @anna wrote:

> Looking at X86 lowering for the vector reduce intrinsics, we do not handle signed zeroes. So, we will need to introduce new intrinsics as `llvm.vector.reduce.fminimum` and `llvm.vector.reduce.fmaximum`, which is similar to existing vector reduce intrinsics but handles signed zeroes and NaN.

My understanding is as follows:
You need to inroduce new reduce intrinsic for fminium and fmaximum as you wrote.
In ExpandReductionsPass replace this intrinsic with reduction where you delegates each comparison to existing fminimum/maximum intrinsics. You just need to propagate nnan and nsz flags to that inrinisics.

With that you will have a correct reduction supporting both NaNs and signed zeros.


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