[PATCH] D151790: [RISCV][NFC] Add isF argument to SchedSEWSet

[Michael Maitland via Phabricator via llvm-commits]

michaelmaitland added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVScheduleV.td:24
+class SchedSEWSet<string mx, bit isF = 0, bit isWidening = 0> {
+  assert !or(!not(isF), !ne(mx, "MF8")), "LMUL shouldn't be MF8 for floating-point";
   defvar t = !cond(!eq(mx, "M1"):  [8, 16, 32, 64],
----------------
craig.topper wrote:
> michaelmaitland wrote:
> > michaelmaitland wrote:
> > > pcwang-thead wrote:
> > > > pcwang-thead wrote:
> > > > > michaelmaitland wrote:
> > > > > > Should we add an assert that LMUL should not be M8 for widening?
> > > > > > Should we add an assert that LMUL should not be M8 for widening?
> > > > > 
> > > > > 
> > > > The scalar operand of reductions can be `M8`, so I think we can't assert that.
> > > What does it mean for a scale operand to be M8? I’m not sure LMUL applies to scalar operands. 
> > > What does it mean for a scale operand to be M8? I’m not sure LMUL applies to scalar operands. 
> > 
> > *Scalar
> The scalar operand is always LMUL=1. But the vector operand of a widening reduction can be LMUL=8 as long at the SEW is less than ELEN. Widening reductions produce a single element result with 2*SEW.
Got it. This change looks good and I have no more questions about this assertion. 


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D151790/new/

https://reviews.llvm.org/D151790