[PATCH] D151790: [RISCV][NFC] Add isF argument to SchedSEWSet

Wang Pengcheng via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed May 31 20:10:05 PDT 2023


pcwang-thead added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVScheduleV.td:24
+class SchedSEWSet<string mx, bit isF = 0, bit isWidening = 0> {
+  assert !or(!not(isF), !ne(mx, "MF8")), "LMUL shouldn't be MF8 for floating-point";
   defvar t = !cond(!eq(mx, "M1"):  [8, 16, 32, 64],
----------------
michaelmaitland wrote:
> Should we add an assert that LMUL should not be M8 for widening?
> Should we add an assert that LMUL should not be M8 for widening?




================
Comment at: llvm/lib/Target/RISCV/RISCVScheduleV.td:24
+class SchedSEWSet<string mx, bit isF = 0, bit isWidening = 0> {
+  assert !or(!not(isF), !ne(mx, "MF8")), "LMUL shouldn't be MF8 for floating-point";
   defvar t = !cond(!eq(mx, "M1"):  [8, 16, 32, 64],
----------------
pcwang-thead wrote:
> michaelmaitland wrote:
> > Should we add an assert that LMUL should not be M8 for widening?
> > Should we add an assert that LMUL should not be M8 for widening?
> 
> 
The scalar operand of reductions can be `M8`, so I think we can't assert that.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151790/new/

https://reviews.llvm.org/D151790



More information about the llvm-commits mailing list