[PATCH] D151850: [RISCV] Model all 3 arithmetic sources of vector FMA at MC layer.

[Craig Topper via Phabricator via llvm-commits]

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For the most part, MC version of vector instructions don't model when
the destination is also a source. This primarily occurs for mask/tail
undisturbed. The MC layer can't see the policy bits so this kind of
makes sense.

We also lumped FMA instructions into this, but the destination of
FMA is an arithmetic source not just an undisturbed value. This needs
to be correct for llvm-mca to understand the dependency for the FMA
instructions. Though every other instruction is still wrong for
tail/mask undisturbed.

This patch models the FMA instructions correctly at the MCA layer.
This necessitates changes to the assembler to offset operand numbers.

We also have to remove hasMergeOp from the pseudo versions. This
property was originally for RISCVAsmPrinter to know to drop the
tail/mask undisturbed value when converting to the MC version. It's
been hijacked by the peepholes in RISCVISelDAGToDAG.cpp too so I had
to make some changes there. I'm going to look at ways to remove this
usage as a follow up.

I've added the extra sched class operand and fixed the operand order
for the scalar read class.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D151850

Files:
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td

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