[PATCH] D149486: [RISCV] Strengthen atomic ordering for sequentially consistent stores

[Paul Kirth via Phabricator via llvm-commits]

paulkirth updated this revision to Diff 527221.
paulkirth added a comment.

Put the trailing fence behind an `experimental` flag.

I'm not sure this is really the best way to go about this. Most of the
"experimental" flags for RISC-V are defined in the tablegen files, but those
are mostly extensions whose entire implementation is experimental, which
doesn't seem to fit well with something that is a fairly minor transform.

Right now the flag also won't be exposed to clang very well. We could add a
module flag and try to plumb this through clang's tablegen, but that also feels
pretty wrong.

If possible I'd appreciate some guidance on the best way to acheive this from
somone with more familiarty with how this should to be done in the RISC-V
backend.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D149486/new/

https://reviews.llvm.org/D149486

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/atomic-load-store.ll

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