[PATCH] D151750: [DAGCombine] `select_cc seteq X, 0, 0, cttz_zero_undef(X) -> and(cttz(X), sizeof(X) - 1)`
Mikhail Gudim via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed May 31 13:17:09 PDT 2023
mgudim added a comment.
I can see two alternatives to the problem you've pointed out.
(1) we could just not do the transformtion at all even before legalization if target doesn't support `cttz`.
(2) This is more complicated:
With my patch the dag looks like this before `lowerSELECT`:
SelectionDAG has 23 nodes:
t0: ch,glue = EntryToken
t2: i64,ch = CopyFromReg t0, Register:i64 %0
t26: i64 = setcc t2, Constant:i64<0>, seteq:ch
t15: i64 = sub Constant:i64<0>, t2
t16: i64 = and t2, t15
t18: i64 = mul t16, Constant:i64<151050438420815295>
t20: i64 = srl t18, Constant:i64<58>
t22: i64 = add ConstantPool:i64<[64 x i8] c"\00\01\02\07\03\0D\08\13\04\19\0E\1C\09\22\14(\05\11\1A&\0F.\1D0\0A\1F#6\152)9?\06\0C\12\18\1B!'\10%-/\1E518>\0B\17 $,47=\16+3<*;:"> 0, t20
t24: i64,ch = load<(load (s8) from constant-pool), zext from i8> t0, t22, undef:i64
t28: i64 = select t26, Constant:i64<64>, t24
t13: i64 = and t28, Constant:i64<63>
t9: ch,glue = CopyToReg t0, Register:i64 $x10, t13
t10: ch = RISCVISD::RET_GLUE t9, Register:i64 $x10, t9:1
Inside `lowerSELECT` we can look at the uses of `t28: i64 = select t26, Constant:i64<64>, t24` and realize that it will be `AND`ed with `63`. So we'll see that
t28: i64 = select t26, Constant:i64<64>, t24
t13: i64 = and t28, Constant:i64<63>
could be replaced with `select c 0, X` (where `X = and(cttz(...), 63)`. This is a profitable reduction for RISCV because that can be turned into `and((c - 1), X)`.
To do this, we'll have to try to see if commuting select with a binop makes the resulting select into something profitable (like when one of the choices is zero). This can work in other cases too.
@craig.topper What do you suggest?
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https://reviews.llvm.org/D151750/new/
https://reviews.llvm.org/D151750
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