[llvm] cf22903 - [RISCV] Change LdPat and StPat from multiclass to class. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed May 31 12:02:13 PDT 2023
Author: Craig Topper
Date: 2023-05-31T12:00:54-07:00
New Revision: cf229033da7e4d9a121b92e6a71197d40210b3e1
URL: https://github.com/llvm/llvm-project/commit/cf229033da7e4d9a121b92e6a71197d40210b3e1
DIFF: https://github.com/llvm/llvm-project/commit/cf229033da7e4d9a121b92e6a71197d40210b3e1.diff
LOG: [RISCV] Change LdPat and StPat from multiclass to class. NFC
These used to contain multiple patterns, but that was simplified
when we moved to using ComplexPattern for load/store address matching.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/lib/Target/RISCV/RISCVInstrInfoA.td
llvm/lib/Target/RISCV/RISCVInstrInfoD.td
llvm/lib/Target/RISCV/RISCVInstrInfoF.td
llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 22bd42b13b765..313ea4c530ae5 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1647,30 +1647,28 @@ def PseudoZEXT_W : Pseudo<(outs GPR:$rd), (ins GPR:$rs), [], "zext.w", "$rd, $rs
/// Loads
-multiclass LdPat<PatFrag LoadOp, RVInst Inst, ValueType vt = XLenVT> {
- def : Pat<(vt (LoadOp (AddrRegImm GPR:$rs1, simm12:$imm12))),
- (Inst GPR:$rs1, simm12:$imm12)>;
-}
-
-defm : LdPat<sextloadi8, LB>;
-defm : LdPat<extloadi8, LBU>; // Prefer unsigned due to no c.lb in Zcb.
-defm : LdPat<sextloadi16, LH>;
-defm : LdPat<extloadi16, LH>;
-defm : LdPat<load, LW, i32>, Requires<[IsRV32]>;
-defm : LdPat<zextloadi8, LBU>;
-defm : LdPat<zextloadi16, LHU>;
+class LdPat<PatFrag LoadOp, RVInst Inst, ValueType vt = XLenVT>
+ : Pat<(vt (LoadOp (AddrRegImm GPR:$rs1, simm12:$imm12))),
+ (Inst GPR:$rs1, simm12:$imm12)>;
+
+def : LdPat<sextloadi8, LB>;
+def : LdPat<extloadi8, LBU>; // Prefer unsigned due to no c.lb in Zcb.
+def : LdPat<sextloadi16, LH>;
+def : LdPat<extloadi16, LH>;
+def : LdPat<load, LW, i32>, Requires<[IsRV32]>;
+def : LdPat<zextloadi8, LBU>;
+def : LdPat<zextloadi16, LHU>;
/// Stores
-multiclass StPat<PatFrag StoreOp, RVInst Inst, RegisterClass StTy,
- ValueType vt> {
- def : Pat<(StoreOp (vt StTy:$rs2), (AddrRegImm GPR:$rs1, simm12:$imm12)),
- (Inst StTy:$rs2, GPR:$rs1, simm12:$imm12)>;
-}
+class StPat<PatFrag StoreOp, RVInst Inst, RegisterClass StTy,
+ ValueType vt>
+ : Pat<(StoreOp (vt StTy:$rs2), (AddrRegImm GPR:$rs1, simm12:$imm12)),
+ (Inst StTy:$rs2, GPR:$rs1, simm12:$imm12)>;
-defm : StPat<truncstorei8, SB, GPR, XLenVT>;
-defm : StPat<truncstorei16, SH, GPR, XLenVT>;
-defm : StPat<store, SW, GPR, i32>, Requires<[IsRV32]>;
+def : StPat<truncstorei8, SB, GPR, XLenVT>;
+def : StPat<truncstorei16, SH, GPR, XLenVT>;
+def : StPat<store, SW, GPR, i32>, Requires<[IsRV32]>;
/// Fences
@@ -1844,15 +1842,15 @@ def : Pat<(binop_allwusers<xor> GPR:$rs1, u32simm12:$imm),
(XORI GPR:$rs1, u32simm12:$imm)>;
/// Loads
-defm : LdPat<sextloadi32, LW, i64>;
-defm : LdPat<extloadi32, LW, i64>;
-defm : LdPat<zextloadi32, LWU, i64>;
-defm : LdPat<load, LD, i64>;
+def : LdPat<sextloadi32, LW, i64>;
+def : LdPat<extloadi32, LW, i64>;
+def : LdPat<zextloadi32, LWU, i64>;
+def : LdPat<load, LD, i64>;
/// Stores
-defm : StPat<truncstorei32, SW, GPR, i64>;
-defm : StPat<store, SD, GPR, i64>;
+def : StPat<truncstorei32, SW, GPR, i64>;
+def : StPat<store, SD, GPR, i64>;
} // Predicates = [IsRV64]
/// readcyclecounter
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td
index 2ec7aa5e87eb4..f2e016602d76e 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td
@@ -43,11 +43,10 @@ multiclass AMO_rr_aq_rl<bits<5> funct5, bits<3> funct3, string opcodestr> {
def _AQ_RL : AMO_rr<funct5, 1, 1, funct3, opcodestr # ".aqrl">;
}
-multiclass AtomicStPat<PatFrag StoreOp, RVInst Inst, RegisterClass StTy,
- ValueType vt = XLenVT> {
- def : Pat<(StoreOp (AddrRegImm GPR:$rs1, simm12:$imm12), (vt StTy:$rs2)),
- (Inst StTy:$rs2, GPR:$rs1, simm12:$imm12)>;
-}
+class AtomicStPat<PatFrag StoreOp, RVInst Inst, RegisterClass StTy,
+ ValueType vt = XLenVT>
+ : Pat<(StoreOp (AddrRegImm GPR:$rs1, simm12:$imm12), (vt StTy:$rs2)),
+ (Inst StTy:$rs2, GPR:$rs1, simm12:$imm12)>;
//===----------------------------------------------------------------------===//
// Instructions
@@ -109,18 +108,18 @@ defm AMOMAXU_D : AMO_rr_aq_rl<0b11100, 0b011, "amomaxu.d">,
// Fences will be inserted for atomic load/stores according to the logic in
// RISCVTargetLowering::{emitLeadingFence,emitTrailingFence}.
let Predicates = [HasAtomicLdSt] in {
- defm : LdPat<atomic_load_8, LB>;
- defm : LdPat<atomic_load_16, LH>;
- defm : LdPat<atomic_load_32, LW>;
+ def : LdPat<atomic_load_8, LB>;
+ def : LdPat<atomic_load_16, LH>;
+ def : LdPat<atomic_load_32, LW>;
- defm : AtomicStPat<atomic_store_8, SB, GPR>;
- defm : AtomicStPat<atomic_store_16, SH, GPR>;
- defm : AtomicStPat<atomic_store_32, SW, GPR>;
+ def : AtomicStPat<atomic_store_8, SB, GPR>;
+ def : AtomicStPat<atomic_store_16, SH, GPR>;
+ def : AtomicStPat<atomic_store_32, SW, GPR>;
}
let Predicates = [HasAtomicLdSt, IsRV64] in {
- defm : LdPat<atomic_load_64, LD, i64>;
- defm : AtomicStPat<atomic_store_64, SD, GPR, i64>;
+ def : LdPat<atomic_load_64, LD, i64>;
+ def : AtomicStPat<atomic_store_64, SD, GPR, i64>;
}
let Predicates = [HasStdExtA] in {
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
index 76605d978da15..9d893e990f7b3 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
@@ -473,11 +473,11 @@ def PseudoFROUND_D : PseudoFROUND<FPR64>;
/// Loads
-defm : LdPat<load, FLD, f64>;
+def : LdPat<load, FLD, f64>;
/// Stores
-defm : StPat<store, FSD, FPR64, f64>;
+def : StPat<store, FSD, FPR64, f64>;
/// Pseudo-instructions needed for the soft-float ABI with RV32D
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
index 0ac5d5177a704..3ae6681bbc82d 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
@@ -627,11 +627,11 @@ def PseudoFROUND_S : PseudoFROUND<FPR32>;
/// Loads
-defm : LdPat<load, FLW, f32>;
+def : LdPat<load, FLW, f32>;
/// Stores
-defm : StPat<store, FSW, FPR32, f32>;
+def : StPat<store, FSW, FPR32, f32>;
} // Predicates = [HasStdExtF]
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
index 274df0245440b..b000f18c57728 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
@@ -402,10 +402,10 @@ def PseudoFROUND_H_INX : PseudoFROUND<FPR16INX>;
let Predicates = [HasStdExtZfhOrZfhmin] in {
/// Loads
-defm : LdPat<load, FLH, f16>;
+def : LdPat<load, FLH, f16>;
/// Stores
-defm : StPat<store, FSH, FPR16, f16>;
+def : StPat<store, FSH, FPR16, f16>;
} // Predicates = [HasStdExtZfhOrZfhmin]
let Predicates = [HasStdExtZhinxOrZhinxmin] in {
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