[PATCH] D151653: [WIP][RISCV] Combine vmv.s.x of constants into vmv.v.i

[Philip Reames via Phabricator via llvm-commits]

reames added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:12352
+        SDValue VL = N->getOperand(2);
+        // If VL is a constant > 0, then change it to 1 to increase
+        // the chances of a toggle being removed by the insert vsetvli
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This looks like something we should maybe be doing for all vmv.s.x instructions.  What happens if you hoist this out of the vmv.v.i specific transform?


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Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:320
+  // A vmv.v.i with VL=1 can be treated in the same way as vmv.s.x, in
+  // that we don't care about LMUL/VL and can expand SEW.
+  // FIXME: We're checking the VL operand here!
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The transform as written here is incorrect.  Consider the case where we have a non-undef pass through operand.  

Take a look at the use of isImplictDef in needVSETVLI.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151653/new/

https://reviews.llvm.org/D151653