[llvm] 9d6f2b1 - [X86] Fix SunnyCove ROB/MicroOpBufferSize

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2023-05-30T15:01:30+01:00
New Revision: 9d6f2b19072e9b8c216350cc5764645891248b8c

URL: https://github.com/llvm/llvm-project/commit/9d6f2b19072e9b8c216350cc5764645891248b8c
DIFF: https://github.com/llvm/llvm-project/commit/9d6f2b19072e9b8c216350cc5764645891248b8c.diff

LOG: [X86] Fix SunnyCove ROB/MicroOpBufferSize

As raised on Issue #62602 - the IceLake scheduler model is still mainly a copy of the SkylakeServer model. This initial commit just fixes the ROB/MicroOpBufferSize to match the size reported on WikiChip/Agner, further fixes to follow in later commits.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86SchedIceLake.td

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86SchedIceLake.td b/llvm/lib/Target/X86/X86SchedIceLake.td
index 4dfeafbca793..ab0e2a95df72 100644
--- a/llvm/lib/Target/X86/X86SchedIceLake.td
+++ b/llvm/lib/Target/X86/X86SchedIceLake.td
@@ -19,7 +19,7 @@ def IceLakeModel : SchedMachineModel {
   // All x86 instructions are modeled as a single micro-op, and Ice Lake can
   // decode 6 instructions per cycle.
   let IssueWidth = 6;
-  let MicroOpBufferSize = 224; // Based on the reorder buffer.
+  let MicroOpBufferSize = 352; // Based on the reorder buffer.
   let LoadLatency = 5;
   let MispredictPenalty = 14;