[PATCH] D151653: [WIP][RISCV] Combine vmv.s.x of constants into vmv.v.i

[Luke Lau via Phabricator via llvm-commits]

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If a vmv.s.x has an undef passthru and the scalar is a constant that
fits into 5 bits, then we can use a vmv.v.i to save an li. If the VL is
a constant > 0, then we can also just set that to 1 to allow for more
toggle removal opportunities.

This patch adds a combine for this, and also teaches the insert vsetvli
pass how to treat vmv.v.i similarly to vmv.s.x, where we can expand the
SEW to avoid a toggle since we're only writing one element. Without the
vsetvli change it actually results in worse codegen because of the
additional toggle.

I'm posting this as WIP since I'd like to get some feedback on how to
check for VL=1 in getDemanded, without actually checking the operands.
As noted in getDemanded, we shouldn't be looking at the VL operand as
it could be stale if the instruction is already lowered.

We could just use the VSETVLIInfo in needVSETVLI to check for this in
the top-to-bottom pass, but then we miss out on the post-lowering
bottom-to-top pass, which catches cases where the vmv.v.i is the first
instruction in an entry block.

I have a feeling checking the VL operand might actually be ok here,
because even if it's stale, the demanded fields for a vmv.v.i with VL=1
should still be the same, regardless of what its actual lowered VL is.

This is just a feeling though, and I would greatly appreciate any input
on this.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D151653

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
  llvm/test/CodeGen/RISCV/rvv/combine-splats.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-shuffle-transpose.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll
  llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll
  llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll

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