[llvm] a3a8cbf - [AMDGPU][AsmParser][NFC] Refine parsing of NamedOperandU32 operands.
Ivan Kosarev via llvm-commits
llvm-commits at lists.llvm.org
Mon May 29 09:01:53 PDT 2023
Author: Ivan Kosarev
Date: 2023-05-29T17:01:44+01:00
New Revision: a3a8cbffcf00bdbf19a15a070313b60c0a9ce342
URL: https://github.com/llvm/llvm-project/commit/a3a8cbffcf00bdbf19a15a070313b60c0a9ce342
DIFF: https://github.com/llvm/llvm-project/commit/a3a8cbffcf00bdbf19a15a070313b60c0a9ce342.diff
LOG: [AMDGPU][AsmParser][NFC] Refine parsing of NamedOperandU32 operands.
Eliminates the need for the custom code in parseCustomOperand().
Part of <https://github.com/llvm/llvm-project/issues/62629>.
Reviewed By: dp
Differential Revision: https://reviews.llvm.org/D150980
Added:
Modified:
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.td
llvm/lib/Target/AMDGPU/SMInstructions.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index e768588f39dc3..7b4817f373b56 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -1761,7 +1761,7 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
AMDGPUOperand::Ptr defaultSMEMOffsetMod() const;
AMDGPUOperand::Ptr defaultFlatOffset() const;
- OperandMatchResultTy parseOModOperand(OperandVector &Operands);
+ OperandMatchResultTy parseOModSI(OperandVector &Operands);
void cvtVOP3(MCInst &Inst, const OperandVector &Operands,
OptionalImmIndexMap &OptionalIdx);
@@ -8048,7 +8048,7 @@ void AMDGPUAsmParser::onBeginOfFile() {
getTargetStreamer().EmitDirectiveAMDGCNTarget();
}
-OperandMatchResultTy AMDGPUAsmParser::parseOModOperand(OperandVector &Operands) {
+OperandMatchResultTy AMDGPUAsmParser::parseOModSI(OperandVector &Operands) {
StringRef Name = getTokenStr();
if (Name == "mul") {
return parseIntWithPrefix("mul", Operands,
@@ -9129,24 +9129,8 @@ AMDGPUAsmParser::parseCustomOperand(OperandVector &Operands, unsigned MCK) {
return parseTokenOp("off", Operands);
case MCK_row_95_en:
return parseTokenOp("row_en", Operands);
- case MCK_ImmCPol:
- return parseCPol(Operands);
case MCK_gds:
return parseNamedBit("gds", Operands, AMDGPUOperand::ImmTyGDS);
- case MCK_ImmNegHi:
- return parseOperandArrayWithPrefix("neg_hi", Operands,
- AMDGPUOperand::ImmTyNegHi);
- case MCK_ImmNegLo:
- return parseOperandArrayWithPrefix("neg_lo", Operands,
- AMDGPUOperand::ImmTyNegLo);
- case MCK_ImmOModSI:
- return parseOModOperand(Operands);
- case MCK_ImmOpSel:
- return parseOperandArrayWithPrefix("op_sel", Operands,
- AMDGPUOperand::ImmTyOpSel);
- case MCK_ImmOpSelHi:
- return parseOperandArrayWithPrefix("op_sel_hi", Operands,
- AMDGPUOperand::ImmTyOpSelHi);
case MCK_tfe:
return parseNamedBit("tfe", Operands, AMDGPUOperand::ImmTyTFE);
}
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
index 47675a78114e3..dfb0b74ef320b 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -1121,15 +1121,6 @@ def SDWAVopcDst : BoolRC {
let PrintMethod = "printVOPDst";
}
-class NamedMatchClass<string CName, bit Optional = 1> : AsmOperandClass {
- let Name = "Imm"#CName;
- let PredicateMethod = "is"#CName;
- let ParserMethod = !if(Optional, "", "parse"#CName);
- let RenderMethod = "addImmOperands";
- let IsOptional = Optional;
- let DefaultMethod = !if(Optional, "default"#CName, ?);
-}
-
class CustomOperandClass<string CName, bit Optional> : AsmOperandClass {
let Name = CName;
let PredicateMethod = "is"#CName;
@@ -1143,6 +1134,7 @@ class CustomOperandProps<bit Optional = 0, string Name = NAME,
AsmOperandClass Class = CustomOperandClass<Name, Optional>> {
string PrintMethod = "print"#Name;
AsmOperandClass ParserMatchClass = Class;
+ string OperandType = "OPERAND_IMMEDIATE";
}
class CustomOperand<ValueType Type, bit Optional = 0, string Name = NAME,
@@ -1173,33 +1165,10 @@ class BitOperandClass<string Id, string Name>
class NamedBitOperand<string Id, string Name = NAME>
: CustomOperand<i1, 1, Name, BitOperandClass<Id, Name>>;
-class DefaultOperand_0<CustomOperand Op>
- : OperandWithDefaultOps<Op.Type, (ops (Op.Type 0))>,
+class DefaultOperand<CustomOperand Op, int Value>
+ : OperandWithDefaultOps<Op.Type, (ops (Op.Type Value))>,
CustomOperandProps<1, Op.ParserMatchClass.Name, Op.ParserMatchClass>;
-class NamedOperandU32<string Name, AsmOperandClass MatchClass> : Operand<i32> {
- let PrintMethod = "print"#Name;
- let ParserMatchClass = MatchClass;
-}
-
-class NamedOperandU32_0<string Name, AsmOperandClass MatchClass> :
- OperandWithDefaultOps<i32, (ops (i32 0))> {
- let PrintMethod = "print"#Name;
- let ParserMatchClass = MatchClass;
-}
-
-class NamedOperandU32Default0<string Name, AsmOperandClass MatchClass> :
- OperandWithDefaultOps<i32, (ops (i32 0))> {
- let PrintMethod = "print"#Name;
- let ParserMatchClass = MatchClass;
-}
-
-class NamedOperandU32Default1<string Name, AsmOperandClass MatchClass> :
- OperandWithDefaultOps<i32, (ops (i32 1))> {
- let PrintMethod = "print"#Name;
- let ParserMatchClass = MatchClass;
-}
-
class SDWAOperandClass<string Id, string Name>
: CustomOperandClass<Name, 1> {
string ImmTy = "AMDGPUOperand::ImmTy"#Name;
@@ -1211,7 +1180,17 @@ class SDWAOperandClass<string Id, string Name>
class SDWAOperand<string Id, string Name = NAME>
: CustomOperand<i32, 1, Name, SDWAOperandClass<Id, Name>>;
-let OperandType = "OPERAND_IMMEDIATE" in {
+class ArrayOperandClass<string Id, string Name>
+ : CustomOperandClass<Name, 1> {
+ string ImmTy = "AMDGPUOperand::ImmTy"#Name;
+ let ParserMethod =
+ "[this](OperandVector &Operands) -> OperandMatchResultTy { "#
+ "return parseOperandArrayWithPrefix(\""#Id#"\", Operands, "#ImmTy#"); }";
+}
+
+class ArrayOperand0<string Id, string Name = NAME>
+ : OperandWithDefaultOps<i32, (ops (i32 0))>,
+ CustomOperandProps<1, Name, ArrayOperandClass<Id, Name>>;
def flat_offset : CustomOperand<i32, 1, "FlatOffset">;
def offset : NamedIntOperand<i32, "offset", "Offset">;
@@ -1220,23 +1199,23 @@ def offset1 : NamedIntOperand<i8, "offset1", "Offset1">;
def gds : NamedBitOperand<"gds", "GDS">;
-def omod : NamedOperandU32<"OModSI", NamedMatchClass<"OModSI">>;
-def omod0 : NamedOperandU32_0<"OModSI", NamedMatchClass<"OModSI">>;
+def omod : CustomOperand<i32, 1, "OModSI">;
+def omod0 : DefaultOperand<omod, 0>;
// We need to make the cases with a default of 0 distinct from no
// default to help deal with some cases where the operand appears
// before a mandatory operand.
def clampmod : NamedBitOperand<"clamp", "ClampSI">;
-def clampmod0 : DefaultOperand_0<clampmod>;
+def clampmod0 : DefaultOperand<clampmod, 0>;
def highmod : NamedBitOperand<"high", "High">;
-def CPol : NamedOperandU32<"CPol", NamedMatchClass<"CPol">>;
-def CPol_0 : NamedOperandU32Default0<"CPol", NamedMatchClass<"CPol">>;
-def CPol_GLC1 : NamedOperandU32Default1<"CPol", NamedMatchClass<"CPol">>;
+def CPol : CustomOperand<i32, 1>;
+def CPol_0 : DefaultOperand<CPol, 0>;
+def CPol_GLC1 : DefaultOperand<CPol, 1>;
def TFE : NamedBitOperand<"tfe">;
def SWZ : NamedBitOperand<"swz">;
-def SWZ_0 : DefaultOperand_0<SWZ>;
+def SWZ_0 : DefaultOperand<SWZ, 0>;
def UNorm : NamedBitOperand<"unorm">;
def DA : NamedBitOperand<"da">;
def R128A16 : CustomOperand<i1, 1>;
@@ -1256,10 +1235,10 @@ def src0_sel : SDWAOperand<"src0_sel", "SDWASrc0Sel">;
def src1_sel : SDWAOperand<"src1_sel", "SDWASrc1Sel">;
def dst_unused : CustomOperand<i32, 1, "SDWADstUnused">;
-def op_sel0 : NamedOperandU32Default0<"OpSel", NamedMatchClass<"OpSel">>;
-def op_sel_hi0 : NamedOperandU32Default0<"OpSelHi", NamedMatchClass<"OpSelHi">>;
-def neg_lo0 : NamedOperandU32Default0<"NegLo", NamedMatchClass<"NegLo">>;
-def neg_hi0 : NamedOperandU32Default0<"NegHi", NamedMatchClass<"NegHi">>;
+def op_sel0 : ArrayOperand0<"op_sel", "OpSel">;
+def op_sel_hi0 : ArrayOperand0<"op_sel_hi", "OpSelHi">;
+def neg_lo0 : ArrayOperand0<"neg_lo", "NegLo">;
+def neg_hi0 : ArrayOperand0<"neg_hi", "NegHi">;
def dpp8 : CustomOperand<i32, 0, "DPP8">;
def dpp_ctrl : CustomOperand<i32, 0, "DPPCtrl">;
@@ -1281,8 +1260,6 @@ def exp_tgt : CustomOperand<i32, 0, "ExpTgt">;
def wait_vdst : NamedIntOperand<i8, "wait_vdst", "WaitVDST">;
def wait_exp : NamedIntOperand<i8, "wait_exp", "WaitEXP">;
-} // End OperandType = "OPERAND_IMMEDIATE"
-
class KImmMatchClass<int size> : AsmOperandClass {
let Name = "KImmFP"#size;
let PredicateMethod = "isKImmFP"#size;
diff --git a/llvm/lib/Target/AMDGPU/SMInstructions.td b/llvm/lib/Target/AMDGPU/SMInstructions.td
index 62c4deae52104..2d0d2f3bb0dfb 100644
--- a/llvm/lib/Target/AMDGPU/SMInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SMInstructions.td
@@ -8,8 +8,7 @@
def smrd_offset_8 : ImmOperand<i32, "SMRDOffset8", 1>;
-let OperandType = "OPERAND_IMMEDIATE",
- EncoderMethod = "getSMEMOffsetEncoding",
+let EncoderMethod = "getSMEMOffsetEncoding",
DecoderMethod = "decodeSMEMOffset" in {
def smem_offset : ImmOperand<i32, "SMEMOffset", 1>;
def smem_offset_mod : NamedIntOperand<i32, "offset", "SMEMOffsetMod">;
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