[PATCH] D127115: [DAGCombine] Make sure combined nodes are added back to the worklist in topological order.

[Amaury SECHET via Phabricator via llvm-commits]

deadalnix updated this revision to Diff 526435.
deadalnix added a comment.

Rebase and fix tests


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D127115/new/

https://reviews.llvm.org/D127115

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/AMDGPU/combine-cond-add-sub.ll
  llvm/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll
  llvm/test/CodeGen/AMDGPU/ds-alignment.ll
  llvm/test/CodeGen/AMDGPU/ds_write2.ll
  llvm/test/CodeGen/AMDGPU/idot4u.ll
  llvm/test/CodeGen/AMDGPU/idot8s.ll
  llvm/test/CodeGen/AMDGPU/idot8u.ll
  llvm/test/CodeGen/AMDGPU/load-local-redundant-copies.ll
  llvm/test/CodeGen/AMDGPU/store-local.128.ll
  llvm/test/CodeGen/AMDGPU/store-local.96.ll
  llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll
  llvm/test/CodeGen/ARM/addsubcarry-promotion.ll
  llvm/test/CodeGen/ARM/icmp-shift-opt.ll
  llvm/test/CodeGen/ARM/reg_sequence.ll
  llvm/test/CodeGen/Hexagon/autohvx/isel-vpackew.ll
  llvm/test/CodeGen/Hexagon/autohvx/mulh.ll
  llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg.ll
  llvm/test/CodeGen/PowerPC/combine-fneg.ll
  llvm/test/CodeGen/PowerPC/select_const.ll
  llvm/test/CodeGen/RISCV/mul.ll
  llvm/test/CodeGen/RISCV/pr58511.ll
  llvm/test/CodeGen/SystemZ/pr36164.ll
  llvm/test/CodeGen/Thumb2/mve-vst3.ll
  llvm/test/CodeGen/X86/2011-10-19-LegelizeLoad.ll
  llvm/test/CodeGen/X86/2012-08-07-CmpISelBug.ll
  llvm/test/CodeGen/X86/addcarry.ll
  llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast.ll
  llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast_from_memory.ll
  llvm/test/CodeGen/X86/avx512-mask-op.ll
  llvm/test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll
  llvm/test/CodeGen/X86/avx512vl-vec-masked-cmp.ll
  llvm/test/CodeGen/X86/bitcast-vector-bool.ll
  llvm/test/CodeGen/X86/const-shift-of-constmasked.ll
  llvm/test/CodeGen/X86/field-extract-use-trunc.ll
  llvm/test/CodeGen/X86/horizontal-sum.ll
  llvm/test/CodeGen/X86/icmp-shift-opt.ll
  llvm/test/CodeGen/X86/insertelement-var-index.ll
  llvm/test/CodeGen/X86/is_fpclass-fp80.ll
  llvm/test/CodeGen/X86/isel-blendi-gettargetconstant.ll
  llvm/test/CodeGen/X86/masked_store.ll
  llvm/test/CodeGen/X86/midpoint-int-vec-512.ll
  llvm/test/CodeGen/X86/movmsk-cmp.ll
  llvm/test/CodeGen/X86/mulvi32.ll
  llvm/test/CodeGen/X86/nontemporal-3.ll
  llvm/test/CodeGen/X86/pmulh.ll
  llvm/test/CodeGen/X86/popcnt.ll
  llvm/test/CodeGen/X86/promote-vec3.ll
  llvm/test/CodeGen/X86/psubus.ll
  llvm/test/CodeGen/X86/shift-mask.ll
  llvm/test/CodeGen/X86/shuffle-strided-with-offset-128.ll
  llvm/test/CodeGen/X86/single_elt_vector_memory_operation.ll
  llvm/test/CodeGen/X86/smax.ll
  llvm/test/CodeGen/X86/smin.ll
  llvm/test/CodeGen/X86/smulo-128-legalisation-lowering.ll
  llvm/test/CodeGen/X86/umax.ll
  llvm/test/CodeGen/X86/umin.ll
  llvm/test/CodeGen/X86/vector-fshl-256.ll
  llvm/test/CodeGen/X86/vector-fshl-512.ll
  llvm/test/CodeGen/X86/vector-fshl-rot-256.ll
  llvm/test/CodeGen/X86/vector-fshl-rot-512.ll
  llvm/test/CodeGen/X86/vector-fshr-256.ll
  llvm/test/CodeGen/X86/vector-fshr-512.ll
  llvm/test/CodeGen/X86/vector-fshr-rot-256.ll
  llvm/test/CodeGen/X86/vector-fshr-rot-512.ll
  llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-2.ll
  llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-3.ll
  llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-4.ll
  llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-5.ll
  llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-6.ll
  llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-7.ll
  llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-8.ll
  llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-2.ll
  llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-3.ll
  llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-4.ll
  llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-5.ll
  llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-6.ll
  llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-7.ll
  llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-8.ll
  llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-2.ll
  llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-3.ll
  llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-4.ll
  llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-5.ll
  llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-6.ll
  llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-7.ll
  llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-8.ll
  llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-2.ll
  llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-5.ll
  llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-6.ll
  llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-7.ll
  llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
  llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
  llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll
  llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-3.ll
  llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-5.ll
  llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-7.ll
  llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
  llvm/test/CodeGen/X86/vector-reduce-and-bool.ll
  llvm/test/CodeGen/X86/vector-reduce-and.ll
  llvm/test/CodeGen/X86/vector-reduce-or-bool.ll
  llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll
  llvm/test/CodeGen/X86/vector-reduce-or.ll
  llvm/test/CodeGen/X86/vector-reduce-xor.ll
  llvm/test/CodeGen/X86/vector-replicaton-i1-mask.ll
  llvm/test/CodeGen/X86/vector-rotate-256.ll
  llvm/test/CodeGen/X86/vector-rotate-512.ll
  llvm/test/CodeGen/X86/vector-shuffle-concatenation.ll
  llvm/test/CodeGen/X86/vector-shuffle-sse4a.ll
  llvm/test/CodeGen/X86/vector-zext.ll
  llvm/test/CodeGen/X86/wide-integer-cmp.ll
  llvm/test/CodeGen/X86/widen-load-of-small-alloca-with-zero-upper-half.ll
  llvm/test/CodeGen/X86/xaluo128.ll
  llvm/test/CodeGen/X86/xor.ll
  llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast.ll