[PATCH] D151596: [RISCV] Teach performCombineVMergeAndVOps to handle instructions FMA instructions.

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck accepted this revision.
frasercrmck added a comment.

LGTM



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Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:3303
   // The vector policy operand may be present for masked intrinsics
-  bool HasVecPolicyOp = RISCVII::hasVecPolicyOp(TrueTSFlags);
   unsigned TrueVLIndex =
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Was this moved just to keep the "HasOp" checks together? I don't mind the change - just asking in case it was part of an earlier diff that got refactored.


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Comment at: llvm/test/CodeGen/RISCV/rvv/vfwmacc-vp.ll:57
+; FIXME: Support this case?
+define <vscale x 1 x float> @vfmacc_vv_nxv1f32_masked__tu(<vscale x 1 x half> %a, <vscale x 1 x half> %b, <vscale x 1 x float> %c, <vscale x 1 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vfmacc_vv_nxv1f32_masked__tu:
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Double underscore in function name?


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https://reviews.llvm.org/D151596