[PATCH] D150324: [X86] Make constant `mul` -> `shl` + `add`/`sub` work for vector types

[Phoebe Wang via Phabricator via llvm-commits]

pengfei added inline comments.


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Comment at: llvm/lib/Target/X86/X86.td:562-564
+def TuningFastImmVectorShift : SubtargetFeature<"tuning-fast-imm-vector-shift",
+                                   "FastImmVectorShift", "true",
+                                   "Vector shifts are fast (2/cycle) as opposed to slow (1/cycle)">;
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Can we get such info from SchedModel rather than put another tuning?


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Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:48653-48655
+  if (isPowerOf2_64(C->getZExtValue())) {
     return SDValue();
+  }
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Remove parentheses.


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Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:48772
+        Opc = ISD::ADD;
+      }
+
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Remove blank line.


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Comment at: llvm/test/CodeGen/X86/omit-urem-of-power-of-two-or-zero-when-comparing-with-zero.ll:323
+; SSE4-NEXT:    paddd %xmm2, %xmm1
+; SSE4-NEXT:    pslld $2, %xmm2
+; SSE4-NEXT:    paddd %xmm1, %xmm2
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IIRC, the intention is to generate `pslld` for new targets. Why this is affected given it's a general turning?

The same for others. I didn't check all, but in most tests we just enable features without specifying a turning target.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D150324/new/

https://reviews.llvm.org/D150324