[llvm] 8a4e367 - [Hexagon] Explicitly make vector subregs have unknown size and offset

[Krzysztof Parzyszek via llvm-commits]

Author: Krzysztof Parzyszek
Date: 2023-05-28T08:32:43-07:00
New Revision: 8a4e3675d88ecd0413d89dea1e3578a4696b05da

URL: https://github.com/llvm/llvm-project/commit/8a4e3675d88ecd0413d89dea1e3578a4696b05da
DIFF: https://github.com/llvm/llvm-project/commit/8a4e3675d88ecd0413d89dea1e3578a4696b05da.diff

LOG: [Hexagon] Explicitly make vector subregs have unknown size and offset

Vector length depends on the HVX mode, so make the size and offset unknown
instead using values for some specific mode.

Added: 
    

Modified: 
    llvm/lib/Target/Hexagon/HexagonRegisterInfo.td

Removed: 
    


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diff  --git a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td
index cb5b6c6e50f5..3a77fcd04e35 100644
--- a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td
+++ b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td
@@ -117,11 +117,11 @@ let Namespace = "Hexagon" in {
 
   def isub_lo  : SubRegIndex<32>;
   def isub_hi  : SubRegIndex<32, 32>;
-  def vsub_lo  : SubRegIndex<512>;
-  def vsub_hi  : SubRegIndex<512, 512>;
-  def vsub_fake: SubRegIndex<512>;
-  def wsub_lo  : SubRegIndex<1024>;
-  def wsub_hi  : SubRegIndex<1024, 1024>;
+  def vsub_lo  : SubRegIndex<-1, -1>;
+  def vsub_hi  : SubRegIndex<-1, -1>;
+  def vsub_fake: SubRegIndex<-1, -1>;
+  def wsub_lo  : SubRegIndex<-1, -1>;
+  def wsub_hi  : SubRegIndex<-1, -1>;
   def subreg_overflow : SubRegIndex<1, 0>;
 
   // Integer registers.