[PATCH] D151434: [RISCV] Generalise shouldExtendTypeInLibcall logic to apply to all <XLEN floats on soft ABIs
Alex Bradbury via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri May 26 14:00:05 PDT 2023
asb updated this revision to Diff 526187.
asb edited the summary of this revision.
asb added a comment.
Rebase, add a helper method for determining if we're targeting a soft FP ABI.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D151434/new/
https://reviews.llvm.org/D151434
Files:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVSubtarget.h
llvm/test/CodeGen/RISCV/half-convert.ll
Index: llvm/test/CodeGen/RISCV/half-convert.ll
===================================================================
--- llvm/test/CodeGen/RISCV/half-convert.ll
+++ llvm/test/CodeGen/RISCV/half-convert.ll
@@ -1828,8 +1828,6 @@
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a0, a0, 16
-; RV32I-NEXT: srli a0, a0, 16
; RV32I-NEXT: call __extendhfsf2 at plt
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lui a1, 913408
@@ -2393,8 +2391,6 @@
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a0, a0, 16
-; RV32I-NEXT: srli a0, a0, 16
; RV32I-NEXT: call __extendhfsf2 at plt
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lui a1, 391168
@@ -3748,8 +3744,6 @@
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a0, a0, 16
-; RV32I-NEXT: srli a0, a0, 16
; RV32I-NEXT: call __extendhfsf2 at plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
@@ -3759,8 +3753,6 @@
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli a0, a0, 48
-; RV64I-NEXT: srli a0, a0, 48
; RV64I-NEXT: call __extendhfsf2 at plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
@@ -4016,8 +4008,6 @@
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32I-NEXT: slli a0, a0, 16
-; RV32I-NEXT: srli a0, a0, 16
; RV32I-NEXT: call __extendhfsf2 at plt
; RV32I-NEXT: call __extendsfdf2 at plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
@@ -4028,11 +4018,7 @@
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli a0, a0, 48
-; RV64I-NEXT: srli a0, a0, 48
; RV64I-NEXT: call __extendhfsf2 at plt
-; RV64I-NEXT: slli a0, a0, 32
-; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: call __extendsfdf2 at plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===================================================================
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -152,6 +152,11 @@
return VLen == 0 ? 65536 : VLen;
}
RISCVABI::ABI getTargetABI() const { return TargetABI; }
+ bool isSoftFPABI() const {
+ return TargetABI == RISCVABI::ABI_LP64 ||
+ TargetABI == RISCVABI::ABI_ILP32 ||
+ TargetABI == RISCVABI::ABI_ILP32E;
+ }
bool isRegisterReservedByUser(Register i) const {
assert(i < RISCV::NUM_TARGET_REGS && "Register out of range");
return UserReservedRegister[i];
Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -15988,9 +15988,9 @@
bool RISCVTargetLowering::shouldExtendTypeInLibCall(EVT Type) const {
// Return false to suppress the unnecessary extensions if the LibCall
- // arguments or return value is f32 type for LP64 ABI.
- RISCVABI::ABI ABI = Subtarget.getTargetABI();
- if (ABI == RISCVABI::ABI_LP64 && (Type == MVT::f32))
+ // arguments or return value is a float narrower than XLEN on a soft FP ABI.
+ if (Subtarget.isSoftFPABI() && (Type.isFloatingPoint() && !Type.isVector() &&
+ Type.getSizeInBits() < Subtarget.getXLen()))
return false;
return true;
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