[llvm] dcd5f31 - [RISCV] Tighten type constraint for RISCVISD::FCLASS_VL.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-05-26T11:49:55-07:00
New Revision: dcd5f312a5885b7bf84dab28b08be7a0ce669529

URL: https://github.com/llvm/llvm-project/commit/dcd5f312a5885b7bf84dab28b08be7a0ce669529
DIFF: https://github.com/llvm/llvm-project/commit/dcd5f312a5885b7bf84dab28b08be7a0ce669529.diff

LOG: [RISCV] Tighten type constraint for RISCVISD::FCLASS_VL.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
index 6ba45a2eef90..ac333e61bb35 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
@@ -133,6 +133,7 @@ def riscv_fclass_vl : SDNode<"RISCVISD::FCLASS_VL",
                              SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisVec<0>,
                                                   SDTCisFP<1>, SDTCisVec<1>,
                                                   SDTCisSameSizeAs<0, 1>,
+                                                  SDTCisSameNumEltsAs<0, 1>,
                                                   SDTCVecEltisVT<2, i1>,
                                                   SDTCisSameNumEltsAs<0, 2>,
                                                   SDTCisVT<3, XLenVT>]>>;