[PATCH] D151470: [RISCV][NFC] Make Reduction scheduler resources SEW aware

[Michael Maitland via Phabricator via llvm-commits]

michaelmaitland added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:3467
     defvar mx = m.MX;
-    defvar WriteVIWRedV_From_MX = !cast<SchedWrite>("WriteVIWRedV_From_" # mx);
-    defm _VS : VPseudoTernaryWithTailPolicy_E<V_M1.vrclass, m.vrclass, V_M1.vrclass, m>,
-               Sched<[WriteVIWRedV_From_MX, ReadVIWRedV, ReadVIWRedV,
-                      ReadVIWRedV, ReadVMask]>;
+    foreach e = SchedSEWSet<mx>.val in {
+      defvar WriteVIWRedV_From_MX_E = !cast<SchedWrite>("WriteVIWRedV_From_" # mx # "_E" # e);
----------------
michaelmaitland wrote:
> craig.topper wrote:
> > michaelmaitland wrote:
> > > craig.topper wrote:
> > > > Should we have a different SEWSet that doesn't 64 in it since we can't widen those?
> > > We would need to do this for all widening instructions, not just reductions? Same for narrowing instructions shouldn't contain the smallest SEW?
> > SEW is the destination for narrowing instructions. SEW=64 can never be the destination of a narrowing instruction.
> > 
> > Do we use SEWSet on any widening or narrowing instructions other than reductions?
> Yes, we do. Let me put together another patch that fixes this for all widening and narrowing instructions.
I take the back. We do not use SEWSet on any other widening or narrowing instructions. I will make the fix in this patch.


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151470/new/

https://reviews.llvm.org/D151470