[llvm] 8f12057 - [ValueTracking] Avoid UB in test (NFC)
Nikita Popov via llvm-commits
llvm-commits at lists.llvm.org
Fri May 26 06:55:30 PDT 2023
Author: Nikita Popov
Date: 2023-05-26T15:55:20+02:00
New Revision: 8f12057e8ec638add17c1ac0019cafbbf4a3ed3b
URL: https://github.com/llvm/llvm-project/commit/8f12057e8ec638add17c1ac0019cafbbf4a3ed3b
DIFF: https://github.com/llvm/llvm-project/commit/8f12057e8ec638add17c1ac0019cafbbf4a3ed3b.diff
LOG: [ValueTracking] Avoid UB in test (NFC)
Don't use br undef, as it is UB.
Added:
Modified:
llvm/test/Analysis/ValueTracking/shift-recurrence-knownbits.ll
Removed:
################################################################################
diff --git a/llvm/test/Analysis/ValueTracking/shift-recurrence-knownbits.ll b/llvm/test/Analysis/ValueTracking/shift-recurrence-knownbits.ll
index 36fbbb52fb9ea..5e9084aac31a3 100644
--- a/llvm/test/Analysis/ValueTracking/shift-recurrence-knownbits.ll
+++ b/llvm/test/Analysis/ValueTracking/shift-recurrence-knownbits.ll
@@ -1,12 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -passes=instcombine -S | FileCheck %s
-define i64 @test_lshr() {
+define i64 @test_lshr(i1 %c) {
; CHECK-LABEL: @test_lshr(
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
-; CHECK-NEXT: br i1 undef, label [[EXIT:%.*]], label [[LOOP]]
+; CHECK-NEXT: br i1 [[C:%.*]], label [[EXIT:%.*]], label [[LOOP]]
; CHECK: exit:
; CHECK-NEXT: ret i64 1023
;
@@ -15,18 +15,18 @@ entry:
loop:
%iv.lshr = phi i64 [1023, %entry], [%iv.lshr.next, %loop]
%iv.lshr.next = lshr i64 %iv.lshr, 1
- br i1 undef, label %exit, label %loop
+ br i1 %c, label %exit, label %loop
exit:
%res = or i64 %iv.lshr, 1023
ret i64 %res
}
-define i64 @test_ashr_zeros() {
+define i64 @test_ashr_zeros(i1 %c) {
; CHECK-LABEL: @test_ashr_zeros(
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
-; CHECK-NEXT: br i1 undef, label [[EXIT:%.*]], label [[LOOP]]
+; CHECK-NEXT: br i1 [[C:%.*]], label [[EXIT:%.*]], label [[LOOP]]
; CHECK: exit:
; CHECK-NEXT: ret i64 1023
;
@@ -35,18 +35,18 @@ entry:
loop:
%iv.ashr = phi i64 [1023, %entry], [%iv.ashr.next, %loop]
%iv.ashr.next = ashr i64 %iv.ashr, 1
- br i1 undef, label %exit, label %loop
+ br i1 %c, label %exit, label %loop
exit:
%res = or i64 %iv.ashr, 1023
ret i64 %res
}
-define i64 @test_ashr_ones() {
+define i64 @test_ashr_ones(i1 %c) {
; CHECK-LABEL: @test_ashr_ones(
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
-; CHECK-NEXT: br i1 undef, label [[EXIT:%.*]], label [[LOOP]]
+; CHECK-NEXT: br i1 [[C:%.*]], label [[EXIT:%.*]], label [[LOOP]]
; CHECK: exit:
; CHECK-NEXT: ret i64 -1
;
@@ -55,19 +55,19 @@ entry:
loop:
%iv.ashr = phi i64 [-1023, %entry], [%iv.ashr.next, %loop]
%iv.ashr.next = ashr i64 %iv.ashr, 1
- br i1 undef, label %exit, label %loop
+ br i1 %c, label %exit, label %loop
exit:
%res = or i64 %iv.ashr, 1023
ret i64 %res
}
; Same as previous, but swapped operands to phi
-define i64 @test_ashr_ones2() {
+define i64 @test_ashr_ones2(i1 %c) {
; CHECK-LABEL: @test_ashr_ones2(
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
-; CHECK-NEXT: br i1 undef, label [[EXIT:%.*]], label [[LOOP]]
+; CHECK-NEXT: br i1 [[C:%.*]], label [[EXIT:%.*]], label [[LOOP]]
; CHECK: exit:
; CHECK-NEXT: ret i64 -1
;
@@ -76,7 +76,7 @@ entry:
loop:
%iv.ashr = phi i64 [%iv.ashr.next, %loop], [-1023, %entry]
%iv.ashr.next = ashr i64 %iv.ashr, 1
- br i1 undef, label %exit, label %loop
+ br i1 %c, label %exit, label %loop
exit:
%res = or i64 %iv.ashr, 1023
ret i64 %res
@@ -84,14 +84,14 @@ exit:
; negative case for when start is unknown
-define i64 @test_ashr_unknown(i64 %start) {
+define i64 @test_ashr_unknown(i1 %c, i64 %start) {
; CHECK-LABEL: @test_ashr_unknown(
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV_ASHR:%.*]] = phi i64 [ [[START:%.*]], [[ENTRY:%.*]] ], [ [[IV_ASHR_NEXT:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[IV_ASHR_NEXT]] = ashr i64 [[IV_ASHR]], 1
-; CHECK-NEXT: br i1 undef, label [[EXIT:%.*]], label [[LOOP]]
+; CHECK-NEXT: br i1 [[C:%.*]], label [[EXIT:%.*]], label [[LOOP]]
; CHECK: exit:
; CHECK-NEXT: [[RES:%.*]] = or i64 [[IV_ASHR]], 1023
; CHECK-NEXT: ret i64 [[RES]]
@@ -101,7 +101,7 @@ entry:
loop:
%iv.ashr = phi i64 [%start, %entry], [%iv.ashr.next, %loop]
%iv.ashr.next = ashr i64 %iv.ashr, 1
- br i1 undef, label %exit, label %loop
+ br i1 %c, label %exit, label %loop
exit:
%res = or i64 %iv.ashr, 1023
ret i64 %res
@@ -109,14 +109,14 @@ exit:
; Negative case where we don't have a (shift) recurrence because the operands
; of the ashr are swapped. (This does end up being a divide recurrence.)
-define i64 @test_ashr_wrong_op(i64 %start) {
+define i64 @test_ashr_wrong_op(i1 %c, i64 %start) {
; CHECK-LABEL: @test_ashr_wrong_op(
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV_ASHR:%.*]] = phi i64 [ [[START:%.*]], [[ENTRY:%.*]] ], [ [[IV_ASHR_NEXT:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[IV_ASHR_NEXT]] = lshr i64 1, [[IV_ASHR]]
-; CHECK-NEXT: br i1 undef, label [[EXIT:%.*]], label [[LOOP]]
+; CHECK-NEXT: br i1 [[C:%.*]], label [[EXIT:%.*]], label [[LOOP]]
; CHECK: exit:
; CHECK-NEXT: [[RES:%.*]] = or i64 [[IV_ASHR]], 1023
; CHECK-NEXT: ret i64 [[RES]]
@@ -126,19 +126,19 @@ entry:
loop:
%iv.ashr = phi i64 [%start, %entry], [%iv.ashr.next, %loop]
%iv.ashr.next = ashr i64 1, %iv.ashr
- br i1 undef, label %exit, label %loop
+ br i1 %c, label %exit, label %loop
exit:
%res = or i64 %iv.ashr, 1023
ret i64 %res
}
-define i64 @test_shl() {
+define i64 @test_shl(i1 %c) {
; CHECK-LABEL: @test_shl(
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
-; CHECK-NEXT: br i1 undef, label [[EXIT:%.*]], label [[LOOP]]
+; CHECK-NEXT: br i1 [[C:%.*]], label [[EXIT:%.*]], label [[LOOP]]
; CHECK: exit:
; CHECK-NEXT: ret i64 0
;
@@ -147,7 +147,7 @@ entry:
loop:
%iv.shl = phi i64 [8, %entry], [%iv.shl.next, %loop]
%iv.shl.next = shl i64 %iv.shl, 1
- br i1 undef, label %exit, label %loop
+ br i1 %c, label %exit, label %loop
exit:
%res = and i64 %iv.shl, 7
ret i64 %res
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