[llvm] 90c4db4 - [RISCV] Don't scalarize vector stores if volatile

[Luke Lau via llvm-commits]

Author: Luke Lau
Date: 2023-05-26T09:34:34+01:00
New Revision: 90c4db4a2ce6b0425dc76dcbdd06b32f52c81792

URL: https://github.com/llvm/llvm-project/commit/90c4db4a2ce6b0425dc76dcbdd06b32f52c81792
DIFF: https://github.com/llvm/llvm-project/commit/90c4db4a2ce6b0425dc76dcbdd06b32f52c81792.diff

LOG: [RISCV] Don't scalarize vector stores if volatile

As noted by @reames in https://reviews.llvm.org/D151211#4373404, we shouldn't
scalarize vector stores of constants if the store is volatile, or vector copies
if either the store or load are volatile.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D151500

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load-store.ll
    llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 10fe699cc9cf..cc1da4975eb4 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -12232,6 +12232,7 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
 
     bool IsScalarizable =
         MemVT.isFixedLengthVector() && ISD::isNormalStore(Store) &&
+        Store->isSimple() &&
         MemVT.getVectorElementType().bitsLE(Subtarget.getXLenVT()) &&
         isPowerOf2_64(MemVT.getSizeInBits()) &&
         MemVT.getSizeInBits() <= Subtarget.getXLen();
@@ -12273,7 +12274,7 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
     //   vle16.v    v8, (a0)
     //   vse16.v    v8, (a1)
     if (auto *L = dyn_cast<LoadSDNode>(Val);
-        L && DCI.isBeforeLegalize() && IsScalarizable &&
+        L && DCI.isBeforeLegalize() && IsScalarizable && L->isSimple() &&
         L->hasNUsesOfValue(1, 0) && L->hasNUsesOfValue(1, 1) &&
         Store->getChain() == SDValue(L, 1) && ISD::isNormalLoad(L) &&
         L->getMemoryVT() == MemVT) {

diff  --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load-store.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load-store.ll
index 7b2381a4b54d..57ea41ee421c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load-store.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load-store.ll
@@ -283,8 +283,7 @@ define void @v2i8_volatile_load(ptr %p, ptr %q) {
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
 ; CHECK-NEXT:    vle8.v v8, (a0)
-; CHECK-NEXT:    lh a0, 0(a0)
-; CHECK-NEXT:    sh a0, 0(a1)
+; CHECK-NEXT:    vse8.v v8, (a1)
 ; CHECK-NEXT:    ret
   %v = load volatile <2 x i8>, ptr %p
   store <2 x i8> %v, ptr %q
@@ -294,8 +293,9 @@ define void @v2i8_volatile_load(ptr %p, ptr %q) {
 define void @v2i8_volatile_store(ptr %p, ptr %q) {
 ; CHECK-LABEL: v2i8_volatile_store:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    lh a0, 0(a0)
-; CHECK-NEXT:    sh a0, 0(a1)
+; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
+; CHECK-NEXT:    vle8.v v8, (a0)
+; CHECK-NEXT:    vse8.v v8, (a1)
 ; CHECK-NEXT:    ret
   %v = load <2 x i8>, ptr %p
   store volatile <2 x i8> %v, ptr %q

diff  --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll
index 846b1b275246..61a358ac471a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll
@@ -325,3 +325,14 @@ define void @store_constant_undef_v2i8(ptr %p) {
   store <2 x i8> <i8 undef, i8 3>, ptr %p
   ret void
 }
+
+define void @store_constant_v2i8_volatile(ptr %p) {
+; CHECK-LABEL: store_constant_v2i8_volatile:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
+; CHECK-NEXT:    vmv.v.i v8, 1
+; CHECK-NEXT:    vse8.v v8, (a0)
+; CHECK-NEXT:    ret
+  store volatile <2 x i8> <i8 1, i8 1>, ptr %p
+  ret void
+}