[PATCH] D151396: [2/N][RISCV] Model vxrm in LLVM intrinsics and machine instructions for RVV fixed-point instructions

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp:22
+#define DEBUG_TYPE "riscv-insert-read-write-csr"
+#define RISCV_INSERT_READ_WRITE_CSR_NAME "RISCV Insert Read/Write CSR Pass"
+
----------------
RISCV -> RISC-V


================
Comment at: llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp:86
+          .addImm(VXRMImm);
+    }
+  }
----------------
We need to add an implicit use of VXRM to the vector instruction. That's how we do it in the InsertVSETVLI pass. See

```
        MI.addOperand(MachineOperand::CreateReg(RISCV::VL, /*isDef*/ false,      
                                                /*isImp*/ true));
```

from `RISCVInsertVSETVLI::emitVSETVLIs`


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:6044
 //===----------------------------------------------------------------------===//
 let Uses = [VXRM], hasSideEffects = 1 in {
+  defm PseudoVAADDU : VPseudoVAALU_VV_VX_RM;
----------------
The Pseudos don't use VXRM until the VXRM write instruction is inserted.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:6046
+  defm PseudoVAADDU : VPseudoVAALU_VV_VX_RM;
+  defm PseudoVAADD : VPseudoVAALU_VV_VX_RM;
+  defm PseudoVASUBU : VPseudoVAALU_VV_VX_RM;
----------------
Line up the colons


================
Comment at: llvm/test/CodeGen/RISCV/O0-pipeline.ll:44
 ; CHECK-NEXT:       RISC-V Insert VSETVLI pass
+; CHECK-NEXT:       RISCV Insert Read/Write CSR Pass
 ; CHECK-NEXT:       Eliminate PHI nodes for register allocation
----------------
RISCV -> RISC-V


================
Comment at: llvm/test/CodeGen/RISCV/rvv/vxrm.mir:30
     dead $x0 = PseudoVSETVLI killed renamable $x10, 197 /* e8, mf8, ta, ma */, implicit-def $vl, implicit-def $vtype
     WriteVXRMImm 0, implicit-def $vxrm
+    renamable $v8 = PseudoVAADD_VV_MF8 killed renamable $v8, killed renamable $v9, 0, $noreg, 3 /* e8 */, implicit $vxrm, implicit $vl, implicit $vtype
----------------
Should we delete the existing WriteVXRMImm instruction from this test?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D151396/new/

https://reviews.llvm.org/D151396