[PATCH] D150969: [AArch64] Try to convert two XTN and two SMLSL to UZP1, SMLSL and SMLSL2

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

> From my personal opinion, I think it is hard to generate uzp1 from above LLVM IR snippet. The legalized DAG is as below.

We have something like "smull(trunc(x), extract_high(y))".  That should be equivalent to "smull2(uzp1(undef,x), y)", I think?


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https://reviews.llvm.org/D150969