[PATCH] D151473: [LegalizeTypes][AArch64][ARM] Teach PromoteIntegerResult to preserve NSW/NUW flags for ADD/SUB.

[Nikita Popov via Phabricator via llvm-commits]

nikic added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp:1251
+    // Preserve nsw flag if the promoted inputs are sign extended.
+    if (N->getFlags().hasNoSignedWrap()) {
+      unsigned OpLEffectiveBits = DAG.ComputeMaxSignificantBits(LHS);
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craig.topper wrote:
> efriedma wrote:
> > Do the flags on the original node actually matter here?  Unless I'm missing something, the logic you're using applies whether or not the original node was marked nsw/nuw.  (e.g. the sum of two zero-extended inputs is always nuw.)
> Good point. At best I guess its a compile time filter. Maybe this argues that this should be in DAGCombine? Or the avgfloor optimization in SimplifyDemandedBits could be made to work use computeKnownBits/ComputeNumSignBits instead of using nuw/nsw?
It seems like combineShiftToAVG() already computes known bits / sign bits anyway, so might as well make use of them...


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  https://reviews.llvm.org/D151473/new/

https://reviews.llvm.org/D151473