[PATCH] D151468: [RISCV] Use v(f)slide1up for shuffle+insert idiom

[Philip Reames via Phabricator via llvm-commits]

reames added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vector-shuffle-vslide1up.ll:45
 ; RV32-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
-; RV32-NEXT:    vmv.s.x v10, a0
-; RV32-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
-; RV32-NEXT:    vwaddu.vv v9, v10, v8
-; RV32-NEXT:    li a0, -1
-; RV32-NEXT:    vwmaccu.vx v9, a0, v8
+; RV32-NEXT:    vmv.s.x v9, a0
+; RV32-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
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I do need to figure out why these aren't matching.  My guess is that we're canonicalizing to a bitcast somewhere, need to track that down.  The delta is an improvement even without the vslide1up match, so I think this can be a separate change.  


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151468/new/

https://reviews.llvm.org/D151468