[PATCH] D151463: [AMDGPU] 4-align SGPR triples

[Jay Foad via Phabricator via llvm-commits]

foad created this revision.
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Previously SGPR triples like s[3:5] were aligned on a 3-SGPR boundary
which has no basis in hardware.

Aligning them on a 4-SGPR boundary is at least justified by the
architecture reference guide which says: "Quad-alignment of SGPRs is
required for operation on more than 64-bits".

Currently there are no instructions that take SGPR triples as operands
so the issue is latent.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D151463

Files:
  llvm/lib/Target/AMDGPU/SIRegisterInfo.td
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-trunc.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
  llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
  llvm/test/CodeGen/AMDGPU/copy-overlap-sgpr-kill.mir
  llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
  llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
  llvm/test/CodeGen/AMDGPU/sgpr-phys-copy.mir
  llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll

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