[PATCH] D149743: [RISCV][CodeGen] Support Zdinx on RV32 codegen

[NAKAMURA Takumi via Phabricator via llvm-commits]

chapuni added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp:278
+    // FIXME: Zdinx RV32 can not work on unaligned scalar memory.
+    const auto &STI = MF->getSubtarget<RISCVSubtarget>();
+    assert(!STI.enableUnalignedScalarMem());
----------------
STI is used only in +Asserts.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D149743/new/

https://reviews.llvm.org/D149743