[llvm] ee1d5f6 - [MC] Check if register is non-null before calling isSubRegisterEq (NFCI)

[Sergei Barannikov via llvm-commits]

Author: Sergei Barannikov
Date: 2023-05-25T08:53:15+03:00
New Revision: ee1d5f637286bda762de76dfc33143abd52c5460

URL: https://github.com/llvm/llvm-project/commit/ee1d5f637286bda762de76dfc33143abd52c5460
DIFF: https://github.com/llvm/llvm-project/commit/ee1d5f637286bda762de76dfc33143abd52c5460.diff

LOG: [MC] Check if register is non-null before calling isSubRegisterEq (NFCI)

D151036 adds an assertions that prohibits iterating over sub- and
super-registers of a null register. This is already the case when
iterating over register units of a null register, and worked by
accident for sub- and super-registers.

Reviewed By: Amir

Differential Revision: https://reviews.llvm.org/D151285

Added: 
    

Modified: 
    bolt/lib/Core/MCPlusBuilder.cpp
    llvm/lib/MC/MCInstrDesc.cpp

Removed: 
    


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diff  --git a/bolt/lib/Core/MCPlusBuilder.cpp b/bolt/lib/Core/MCPlusBuilder.cpp
index 5ee79c64bc9c4..027cef1063ee3 100644
--- a/bolt/lib/Core/MCPlusBuilder.cpp
+++ b/bolt/lib/Core/MCPlusBuilder.cpp
@@ -425,7 +425,7 @@ bool MCPlusBuilder::hasDefOfPhysReg(const MCInst &MI, unsigned Reg) const {
 bool MCPlusBuilder::hasUseOfPhysReg(const MCInst &MI, unsigned Reg) const {
   const MCInstrDesc &InstInfo = Info->get(MI.getOpcode());
   for (int I = InstInfo.NumDefs; I < InstInfo.NumOperands; ++I)
-    if (MI.getOperand(I).isReg() &&
+    if (MI.getOperand(I).isReg() && MI.getOperand(I).getReg() &&
         RegInfo->isSubRegisterEq(Reg, MI.getOperand(I).getReg()))
       return true;
   for (MCPhysReg ImplicitUse : InstInfo.implicit_uses()) {

diff  --git a/llvm/lib/MC/MCInstrDesc.cpp b/llvm/lib/MC/MCInstrDesc.cpp
index b800456edc68f..45c5ea73f7f64 100644
--- a/llvm/lib/MC/MCInstrDesc.cpp
+++ b/llvm/lib/MC/MCInstrDesc.cpp
@@ -40,7 +40,7 @@ bool MCInstrDesc::hasImplicitDefOfPhysReg(unsigned Reg,
 bool MCInstrDesc::hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
                                   const MCRegisterInfo &RI) const {
   for (int i = 0, e = NumDefs; i != e; ++i)
-    if (MI.getOperand(i).isReg() &&
+    if (MI.getOperand(i).isReg() && MI.getOperand(i).getReg() &&
         RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg()))
       return true;
   if (variadicOpsAreDefs())