[PATCH] D151176: [RISCV] Custom lower vector llvm.is.fpclass to vfclass.v

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed May 24 20:55:04 PDT 2023


craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4396
+      SDValue FPCLASS =
+          DAG.getNode(RISCVISD::FPCLASS, DL, DstVT, Op0, Op->getFlags());
+      SDValue AND = DAG.getNode(ISD::AND, DL, DstVT, FPCLASS,
----------------
Reuse `RISCVISD::FPCLASS_VL` here. You can pass `DAG.getRegister(RISCV::X0, XLenVT)` as the VL.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4424
+
+    SDValue VMSEQ = DAG.getNode(RISCVISD::SETCC_VL, DL, ContainerVT,
+                                {AND, SplatZero, DAG.getCondCode(ISD::SETNE),
----------------
This is a VMSNE


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151176/new/

https://reviews.llvm.org/D151176



More information about the llvm-commits mailing list