[llvm] 11fbd0c - [PowerPC] Remove asserts from the disassembler.

[Stefan Pintilie via llvm-commits]

Author: Stefan Pintilie
Date: 2023-05-24T13:22:23-04:00
New Revision: 11fbd0c6abc9c47714247b58d9d8b0ef12bf1a4e

URL: https://github.com/llvm/llvm-project/commit/11fbd0c6abc9c47714247b58d9d8b0ef12bf1a4e
DIFF: https://github.com/llvm/llvm-project/commit/11fbd0c6abc9c47714247b58d9d8b0ef12bf1a4e.diff

LOG: [PowerPC] Remove asserts from the disassembler.

My previous patch had added a couple of asserts to the disassembler.
The problem with this is that the disassembler is not just used for the
text section it is also used to disassemble the data section of an
object where the bytes do not necessarily represent instructions. If the
data in the data section happens to look like an illegal instruction
then llvm-objdump will assert on data because it is finding an illegal
instruction that is not actually an instruction at all.

Reviewed By: nemanjai, #powerpc

Differential Revision: https://reviews.llvm.org/D149711

Added: 
    llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp-invalid.txt

Modified: 
    llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp b/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
index 3d9a9ccb18659..0c6c17d5a0b68 100644
--- a/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
+++ b/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
@@ -83,7 +83,8 @@ static DecodeStatus decodeDirectBrTarget(MCInst &Inst, unsigned Imm,
 template <std::size_t N>
 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo,
                                         const MCPhysReg (&Regs)[N]) {
-  assert(RegNo < N && "Invalid register number");
+  if (RegNo >= N)
+    return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createReg(Regs[RegNo]));
   return MCDisassembler::Success;
 }
@@ -115,8 +116,8 @@ static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo,
 static DecodeStatus DecodeFpRCRegisterClass(MCInst &Inst, uint64_t RegNo,
                                             uint64_t Address,
                                             const MCDisassembler *Decoder) {
-  assert(RegNo <= 30 && "Expecting a register number no more than 30.");
-  assert((RegNo & 1) == 0 && "Expecting an even register number.");
+  if (RegNo > 30 || (RegNo & 1))
+    return MCDisassembler::Fail;
   return decodeRegisterClass(Inst, RegNo >> 1, FpRegs);
 }
 
@@ -348,7 +349,8 @@ static DecodeStatus decodeCRBitMOperand(MCInst &Inst, uint64_t Imm,
   // The cr bit encoding is 0x80 >> cr_reg_num.
 
   unsigned Zeros = llvm::countr_zero(Imm);
-  assert(Zeros < 8 && "Invalid CR bit value");
+  if (Zeros >= 8)
+    return MCDisassembler::Fail;
 
   Inst.addOperand(MCOperand::createReg(CRRegs[7 - Zeros]));
   return MCDisassembler::Success;

diff  --git a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp-invalid.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp-invalid.txt
new file mode 100644
index 0000000000000..5ea101cf9af39
--- /dev/null
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp-invalid.txt
@@ -0,0 +1,7 @@
+# RUN: llvm-mc --disassemble %s -mcpu=pwr10 -triple \
+# RUN:   powerpc64-unknown-linux-gnu < %s 2>&1 | FileCheck %s
+
+# Regsiter for DSUBQ cannot be greater than 30.
+# CHECK-NOT: dsubq 0, 6, 31
+# CHECK: warning: invalid instruction encoding
+0xfc 0x06 0xfc 0x04