[PATCH] D151347: [RISCV] Use vfslide1down for build_vectors of non-constant floats

[Philip Reames via Phabricator via llvm-commits]

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This adds the vfslide1down (and vfslide1up for consistency) nodes.  These mostly parallel the existing vslide1down/up nodes.  (See note below on instruction semantics.)  We then use the vfslide1down in build_vector lowering instead of going through the stack.

The specification is more than a bit vague on the meaning of these instructions.  All we're given is "The vfslide1down instruction is defined analogously, but sources its scalar argument from an f register.".  The challenge comes from the fact that vslide1down has truncation and sign extension defined in terms of XLEN.  This seems unlikely to be correct for a floating point op, so I'm assuming that should be FLEN on the floating point version.  If true, then all legal types fall into the truncation case, and we don't have to figure out what the analogous floating point operation to sign extension is for the FLEN < SEW case.

I'll note that V doesn't have any issue here since V implies F and D.  Zve64f could potentially have a problem, but I wasn't able to write a test case which got here since f64 was not a legal type and we scalarized/split before lowering the build_vector.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D151347

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll

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