[llvm] 5a8ce74 - [RISCV] Add test coverage for buildvector of FP values

[Philip Reames via llvm-commits]

Author: Philip Reames
Date: 2023-05-24T07:47:23-07:00
New Revision: 5a8ce742fc1861b99ad4610941f955d87d1a3e9d

URL: https://github.com/llvm/llvm-project/commit/5a8ce742fc1861b99ad4610941f955d87d1a3e9d
DIFF: https://github.com/llvm/llvm-project/commit/5a8ce742fc1861b99ad4610941f955d87d1a3e9d.diff

LOG: [RISCV] Add test coverage for buildvector of FP values

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
index 0d3169d75cb6..d4de78ba1a46 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
@@ -287,3 +287,92 @@ define dso_local void @splat_load_licm(float* %0) {
 8:                                                ; preds = %2
   ret void
 }
+
+define <2 x half> @buildvec_v2f16(half %a, half %b) {
+; CHECK-LABEL: buildvec_v2f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    fsh fa1, 14(sp)
+; CHECK-NEXT:    fsh fa0, 12(sp)
+; CHECK-NEXT:    addi a0, sp, 12
+; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    ret
+  %v1 = insertelement <2 x half> poison, half %a, i64 0
+  %v2 = insertelement <2 x half> %v1, half %b, i64 1
+  ret <2 x half> %v2
+}
+
+define <2 x float> @buildvec_v2f32(float %a, float %b) {
+; CHECK-LABEL: buildvec_v2f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    fsw fa1, 12(sp)
+; CHECK-NEXT:    fsw fa0, 8(sp)
+; CHECK-NEXT:    addi a0, sp, 8
+; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT:    vle32.v v8, (a0)
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    ret
+  %v1 = insertelement <2 x float> poison, float %a, i64 0
+  %v2 = insertelement <2 x float> %v1, float %b, i64 1
+  ret <2 x float> %v2
+}
+
+define <2 x double> @buildvec_v2f64(double %a, double %b) {
+; CHECK-LABEL: buildvec_v2f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    fsd fa1, 8(sp)
+; CHECK-NEXT:    fsd fa0, 0(sp)
+; CHECK-NEXT:    mv a0, sp
+; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT:    vle64.v v8, (a0)
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    ret
+  %v1 = insertelement <2 x double> poison, double %a, i64 0
+  %v2 = insertelement <2 x double> %v1, double %b, i64 1
+  ret <2 x double> %v2
+}
+
+define <2 x double> @buildvec_v2f64_b(double %a, double %b) {
+; CHECK-LABEL: buildvec_v2f64_b:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    fsd fa1, 8(sp)
+; CHECK-NEXT:    fsd fa0, 0(sp)
+; CHECK-NEXT:    mv a0, sp
+; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT:    vle64.v v8, (a0)
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    ret
+  %v1 = insertelement <2 x double> poison, double %b, i64 1
+  %v2 = insertelement <2 x double> %v1, double %a, i64 0
+  ret <2 x double> %v2
+}
+
+define <4 x float> @buildvec_v4f32(float %a, float %b, float %c, float %d) {
+; CHECK-LABEL: buildvec_v4f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    fsw fa3, 12(sp)
+; CHECK-NEXT:    fsw fa2, 8(sp)
+; CHECK-NEXT:    fsw fa1, 4(sp)
+; CHECK-NEXT:    fsw fa0, 0(sp)
+; CHECK-NEXT:    mv a0, sp
+; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT:    vle32.v v8, (a0)
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    ret
+  %v1 = insertelement <4 x float> poison, float %a, i64 0
+  %v2 = insertelement <4 x float> %v1, float %b, i64 1
+  %v3 = insertelement <4 x float> %v2, float %c, i64 2
+  %v4 = insertelement <4 x float> %v3, float %d, i64 3
+  ret <4 x float> %v4
+}