[PATCH] D150963: [AArch64] merge scaled and unscaled zero narrow stores.

[Florian Hahn via Phabricator via llvm-commits]

fhahn added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp:767
+  bool IsScaledRtMI = !TII->hasUnscaledLdStOffset(RtMI->getOpcode());
+  int OffsetStrideRtMI = IsScaledRtMI ? TII->getMemScale(*RtMI) : 1;
+  // Normalise final offset to be expressed in bytes.
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Instead we could just assign OffsetStrideRtMI in the `if` above (like `RtMI`) using the already computed strides?


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Comment at: llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp:770
+  if (IsScaledRtMI) {
+    OffsetImm *= OffsetStrideRtMI;
+  }
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There's no need to check for IsScaled here, as we will just multiply with 1 in the unscaled case


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D150963/new/

https://reviews.llvm.org/D150963