[llvm] 1f7c174 - [RISCV] Expand rotate by non-constant for XTHeadBb during lowering.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue May 23 16:31:38 PDT 2023
Author: Craig Topper
Date: 2023-05-23T16:31:22-07:00
New Revision: 1f7c1741d6e294fcce754a22ad96a6352f3e1f21
URL: https://github.com/llvm/llvm-project/commit/1f7c1741d6e294fcce754a22ad96a6352f3e1f21
DIFF: https://github.com/llvm/llvm-project/commit/1f7c1741d6e294fcce754a22ad96a6352f3e1f21.diff
LOG: [RISCV] Expand rotate by non-constant for XTHeadBb during lowering.
Avoids multi instruction isel patterns and enables mask optimizations
on shift amount.
Reviewed By: philipp.tomsich
Differential Revision: https://reviews.llvm.org/D151263
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
llvm/test/CodeGen/RISCV/rotl-rotr.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 766356b07bb2d..27540fc1d0119 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -285,10 +285,13 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction({ISD::SHL_PARTS, ISD::SRL_PARTS, ISD::SRA_PARTS}, XLenVT,
Custom);
- if (Subtarget.hasStdExtZbb() || Subtarget.hasStdExtZbkb() ||
- Subtarget.hasVendorXTHeadBb()) {
+ if (Subtarget.hasStdExtZbb() || Subtarget.hasStdExtZbkb()) {
if (Subtarget.is64Bit())
setOperationAction({ISD::ROTL, ISD::ROTR}, MVT::i32, Custom);
+ } else if (Subtarget.hasVendorXTHeadBb()) {
+ if (Subtarget.is64Bit())
+ setOperationAction({ISD::ROTL, ISD::ROTR}, MVT::i32, Custom);
+ setOperationAction({ISD::ROTL, ISD::ROTR}, XLenVT, Custom);
} else {
setOperationAction({ISD::ROTL, ISD::ROTR}, XLenVT, Expand);
}
@@ -4418,6 +4421,15 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
return lowerShiftRightParts(Op, DAG, true);
case ISD::SRL_PARTS:
return lowerShiftRightParts(Op, DAG, false);
+ case ISD::ROTL:
+ case ISD::ROTR:
+ assert(Subtarget.hasVendorXTHeadBb() &&
+ !(Subtarget.hasStdExtZbb() || Subtarget.hasStdExtZbkb()) &&
+ "Unexpected custom legalization");
+ // XTHeadBb only supports rotate by constant.
+ if (!isa<ConstantSDNode>(Op.getOperand(1)))
+ return SDValue();
+ return Op;
case ISD::BITCAST: {
SDLoc DL(Op);
EVT VT = Op.getValueType();
@@ -9032,6 +9044,12 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
case ISD::ROTR:
assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
"Unexpected custom legalisation");
+ assert((Subtarget.hasStdExtZbb() || Subtarget.hasStdExtZbkb() ||
+ Subtarget.hasVendorXTHeadBb()) &&
+ "Unexpected custom legalization");
+ if (!isa<ConstantSDNode>(N->getOperand(1)) &&
+ !(Subtarget.hasStdExtZbb() || Subtarget.hasStdExtZbkb()))
+ return;
Results.push_back(customLegalizeToWOp(N, DAG));
break;
case ISD::CTTZ:
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
index e7b63cb171897..d2a519868f1e1 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
@@ -598,12 +598,6 @@ def : PatGprImm<rotr, TH_SRRI, uimmlog2xlen>;
// it can be implemented with th.srri by negating the immediate.
def : Pat<(rotl GPR:$rs1, uimmlog2xlen:$shamt),
(TH_SRRI GPR:$rs1, (ImmSubFromXLen uimmlog2xlen:$shamt))>;
-def : Pat<(rotr GPR:$rs1, GPR:$rs2),
- (OR (SRL GPR:$rs1, GPR:$rs2),
- (SLL GPR:$rs1, (SUB X0, GPR:$rs2)))>;
-def : Pat<(rotl GPR:$rs1, GPR:$rs2),
- (OR (SLL GPR:$rs1, GPR:$rs2),
- (SRL GPR:$rs1, (SUB X0, GPR:$rs2)))>;
def : Pat<(sext_inreg GPR:$rs1, i32), (TH_EXT GPR:$rs1, 31, 0)>;
def : Pat<(sext_inreg GPR:$rs1, i16), (TH_EXT GPR:$rs1, 15, 0)>;
def : Pat<(sext_inreg GPR:$rs1, i8), (TH_EXT GPR:$rs1, 7, 0)>;
@@ -617,12 +611,6 @@ let Predicates = [HasVendorXTHeadBb, IsRV64] in {
def : PatGprImm<riscv_rorw, TH_SRRIW, uimm5>;
def : Pat<(riscv_rolw GPR:$rs1, uimm5:$rs2),
(TH_SRRIW GPR:$rs1, (ImmSubFrom32 uimm5:$rs2))>;
-def : Pat<(riscv_rorw i64:$rs1, i64:$rs2),
- (OR (SRLW i64:$rs1, i64:$rs2),
- (SLLW i64:$rs1, (SUB X0, i64:$rs2)))>;
-def : Pat<(riscv_rolw i64:$rs1, i64:$rs2),
- (OR (SLLW i64:$rs1, i64:$rs2),
- (SRLW i64:$rs1, (SUB X0, i64:$rs2)))>;
def : Pat<(sra (bswap i64:$rs1), (i64 32)),
(TH_REVW i64:$rs1)>;
def : Pat<(binop_allwusers<srl> (bswap i64:$rs1), (i64 32)),
diff --git a/llvm/test/CodeGen/RISCV/rotl-rotr.ll b/llvm/test/CodeGen/RISCV/rotl-rotr.ll
index 74bc333010dd5..160d62ef0818d 100644
--- a/llvm/test/CodeGen/RISCV/rotl-rotr.ll
+++ b/llvm/test/CodeGen/RISCV/rotl-rotr.ll
@@ -56,7 +56,7 @@ define i32 @rotl_32(i32 %x, i32 %y) nounwind {
; RV64XTHEADBB-LABEL: rotl_32:
; RV64XTHEADBB: # %bb.0:
; RV64XTHEADBB-NEXT: sllw a2, a0, a1
-; RV64XTHEADBB-NEXT: neg a1, a1
+; RV64XTHEADBB-NEXT: negw a1, a1
; RV64XTHEADBB-NEXT: srlw a0, a0, a1
; RV64XTHEADBB-NEXT: or a0, a2, a0
; RV64XTHEADBB-NEXT: ret
@@ -105,7 +105,7 @@ define i32 @rotr_32(i32 %x, i32 %y) nounwind {
; RV64XTHEADBB-LABEL: rotr_32:
; RV64XTHEADBB: # %bb.0:
; RV64XTHEADBB-NEXT: srlw a2, a0, a1
-; RV64XTHEADBB-NEXT: neg a1, a1
+; RV64XTHEADBB-NEXT: negw a1, a1
; RV64XTHEADBB-NEXT: sllw a0, a0, a1
; RV64XTHEADBB-NEXT: or a0, a2, a0
; RV64XTHEADBB-NEXT: ret
@@ -253,7 +253,7 @@ define i64 @rotl_64(i64 %x, i64 %y) nounwind {
; RV64XTHEADBB-LABEL: rotl_64:
; RV64XTHEADBB: # %bb.0:
; RV64XTHEADBB-NEXT: sll a2, a0, a1
-; RV64XTHEADBB-NEXT: neg a1, a1
+; RV64XTHEADBB-NEXT: negw a1, a1
; RV64XTHEADBB-NEXT: srl a0, a0, a1
; RV64XTHEADBB-NEXT: or a0, a2, a0
; RV64XTHEADBB-NEXT: ret
@@ -401,7 +401,7 @@ define i64 @rotr_64(i64 %x, i64 %y) nounwind {
; RV64XTHEADBB-LABEL: rotr_64:
; RV64XTHEADBB: # %bb.0:
; RV64XTHEADBB-NEXT: srl a2, a0, a1
-; RV64XTHEADBB-NEXT: neg a1, a1
+; RV64XTHEADBB-NEXT: negw a1, a1
; RV64XTHEADBB-NEXT: sll a0, a0, a1
; RV64XTHEADBB-NEXT: or a0, a2, a0
; RV64XTHEADBB-NEXT: ret
@@ -450,7 +450,7 @@ define i32 @rotl_32_mask(i32 %x, i32 %y) nounwind {
; RV64XTHEADBB-LABEL: rotl_32_mask:
; RV64XTHEADBB: # %bb.0:
; RV64XTHEADBB-NEXT: sllw a2, a0, a1
-; RV64XTHEADBB-NEXT: neg a1, a1
+; RV64XTHEADBB-NEXT: negw a1, a1
; RV64XTHEADBB-NEXT: srlw a0, a0, a1
; RV64XTHEADBB-NEXT: or a0, a2, a0
; RV64XTHEADBB-NEXT: ret
@@ -500,7 +500,7 @@ define i32 @rotl_32_mask_and_63_and_31(i32 %x, i32 %y) nounwind {
; RV64XTHEADBB-LABEL: rotl_32_mask_and_63_and_31:
; RV64XTHEADBB: # %bb.0:
; RV64XTHEADBB-NEXT: sllw a2, a0, a1
-; RV64XTHEADBB-NEXT: neg a1, a1
+; RV64XTHEADBB-NEXT: negw a1, a1
; RV64XTHEADBB-NEXT: srlw a0, a0, a1
; RV64XTHEADBB-NEXT: or a0, a2, a0
; RV64XTHEADBB-NEXT: ret
@@ -548,7 +548,7 @@ define i32 @rotl_32_mask_or_64_or_32(i32 %x, i32 %y) nounwind {
; RV64XTHEADBB-LABEL: rotl_32_mask_or_64_or_32:
; RV64XTHEADBB: # %bb.0:
; RV64XTHEADBB-NEXT: sllw a2, a0, a1
-; RV64XTHEADBB-NEXT: neg a1, a1
+; RV64XTHEADBB-NEXT: negw a1, a1
; RV64XTHEADBB-NEXT: srlw a0, a0, a1
; RV64XTHEADBB-NEXT: or a0, a2, a0
; RV64XTHEADBB-NEXT: ret
@@ -599,7 +599,7 @@ define i32 @rotr_32_mask(i32 %x, i32 %y) nounwind {
; RV64XTHEADBB-LABEL: rotr_32_mask:
; RV64XTHEADBB: # %bb.0:
; RV64XTHEADBB-NEXT: srlw a2, a0, a1
-; RV64XTHEADBB-NEXT: neg a1, a1
+; RV64XTHEADBB-NEXT: negw a1, a1
; RV64XTHEADBB-NEXT: sllw a0, a0, a1
; RV64XTHEADBB-NEXT: or a0, a2, a0
; RV64XTHEADBB-NEXT: ret
@@ -649,7 +649,7 @@ define i32 @rotr_32_mask_and_63_and_31(i32 %x, i32 %y) nounwind {
; RV64XTHEADBB-LABEL: rotr_32_mask_and_63_and_31:
; RV64XTHEADBB: # %bb.0:
; RV64XTHEADBB-NEXT: srlw a2, a0, a1
-; RV64XTHEADBB-NEXT: neg a1, a1
+; RV64XTHEADBB-NEXT: negw a1, a1
; RV64XTHEADBB-NEXT: sllw a0, a0, a1
; RV64XTHEADBB-NEXT: or a0, a2, a0
; RV64XTHEADBB-NEXT: ret
@@ -695,7 +695,7 @@ define i32 @rotr_32_mask_or_64_or_32(i32 %x, i32 %y) nounwind {
; RV64XTHEADBB-LABEL: rotr_32_mask_or_64_or_32:
; RV64XTHEADBB: # %bb.0:
; RV64XTHEADBB-NEXT: srlw a2, a0, a1
-; RV64XTHEADBB-NEXT: neg a1, a1
+; RV64XTHEADBB-NEXT: negw a1, a1
; RV64XTHEADBB-NEXT: sllw a0, a0, a1
; RV64XTHEADBB-NEXT: or a0, a2, a0
; RV64XTHEADBB-NEXT: ret
@@ -839,7 +839,7 @@ define i64 @rotl_64_mask(i64 %x, i64 %y) nounwind {
; RV64XTHEADBB-LABEL: rotl_64_mask:
; RV64XTHEADBB: # %bb.0:
; RV64XTHEADBB-NEXT: sll a2, a0, a1
-; RV64XTHEADBB-NEXT: neg a1, a1
+; RV64XTHEADBB-NEXT: negw a1, a1
; RV64XTHEADBB-NEXT: srl a0, a0, a1
; RV64XTHEADBB-NEXT: or a0, a2, a0
; RV64XTHEADBB-NEXT: ret
@@ -985,7 +985,7 @@ define i64 @rotl_64_mask_and_127_and_63(i64 %x, i64 %y) nounwind {
; RV64XTHEADBB-LABEL: rotl_64_mask_and_127_and_63:
; RV64XTHEADBB: # %bb.0:
; RV64XTHEADBB-NEXT: sll a2, a0, a1
-; RV64XTHEADBB-NEXT: neg a1, a1
+; RV64XTHEADBB-NEXT: negw a1, a1
; RV64XTHEADBB-NEXT: srl a0, a0, a1
; RV64XTHEADBB-NEXT: or a0, a2, a0
; RV64XTHEADBB-NEXT: ret
@@ -1035,7 +1035,7 @@ define i64 @rotl_64_mask_or_128_or_64(i64 %x, i64 %y) nounwind {
; RV64XTHEADBB-LABEL: rotl_64_mask_or_128_or_64:
; RV64XTHEADBB: # %bb.0:
; RV64XTHEADBB-NEXT: sll a2, a0, a1
-; RV64XTHEADBB-NEXT: neg a1, a1
+; RV64XTHEADBB-NEXT: negw a1, a1
; RV64XTHEADBB-NEXT: srl a0, a0, a1
; RV64XTHEADBB-NEXT: or a0, a2, a0
; RV64XTHEADBB-NEXT: ret
@@ -1179,7 +1179,7 @@ define i64 @rotr_64_mask(i64 %x, i64 %y) nounwind {
; RV64XTHEADBB-LABEL: rotr_64_mask:
; RV64XTHEADBB: # %bb.0:
; RV64XTHEADBB-NEXT: srl a2, a0, a1
-; RV64XTHEADBB-NEXT: neg a1, a1
+; RV64XTHEADBB-NEXT: negw a1, a1
; RV64XTHEADBB-NEXT: sll a0, a0, a1
; RV64XTHEADBB-NEXT: or a0, a2, a0
; RV64XTHEADBB-NEXT: ret
@@ -1325,7 +1325,7 @@ define i64 @rotr_64_mask_and_127_and_63(i64 %x, i64 %y) nounwind {
; RV64XTHEADBB-LABEL: rotr_64_mask_and_127_and_63:
; RV64XTHEADBB: # %bb.0:
; RV64XTHEADBB-NEXT: srl a2, a0, a1
-; RV64XTHEADBB-NEXT: neg a1, a1
+; RV64XTHEADBB-NEXT: negw a1, a1
; RV64XTHEADBB-NEXT: sll a0, a0, a1
; RV64XTHEADBB-NEXT: or a0, a2, a0
; RV64XTHEADBB-NEXT: ret
@@ -1371,7 +1371,7 @@ define i64 @rotr_64_mask_or_128_or_64(i64 %x, i64 %y) nounwind {
; RV64XTHEADBB-LABEL: rotr_64_mask_or_128_or_64:
; RV64XTHEADBB: # %bb.0:
; RV64XTHEADBB-NEXT: srl a2, a0, a1
-; RV64XTHEADBB-NEXT: neg a1, a1
+; RV64XTHEADBB-NEXT: negw a1, a1
; RV64XTHEADBB-NEXT: sll a0, a0, a1
; RV64XTHEADBB-NEXT: or a0, a2, a0
; RV64XTHEADBB-NEXT: ret
@@ -1423,11 +1423,10 @@ define signext i32 @rotl_32_mask_shared(i32 signext %a, i32 signext %b, i32 sign
;
; RV32XTHEADBB-LABEL: rotl_32_mask_shared:
; RV32XTHEADBB: # %bb.0:
-; RV32XTHEADBB-NEXT: andi a3, a2, 31
-; RV32XTHEADBB-NEXT: sll a4, a0, a3
-; RV32XTHEADBB-NEXT: neg a3, a3
-; RV32XTHEADBB-NEXT: srl a0, a0, a3
-; RV32XTHEADBB-NEXT: or a0, a4, a0
+; RV32XTHEADBB-NEXT: sll a3, a0, a2
+; RV32XTHEADBB-NEXT: neg a4, a2
+; RV32XTHEADBB-NEXT: srl a0, a0, a4
+; RV32XTHEADBB-NEXT: or a0, a3, a0
; RV32XTHEADBB-NEXT: sll a1, a1, a2
; RV32XTHEADBB-NEXT: add a0, a0, a1
; RV32XTHEADBB-NEXT: ret
@@ -1435,7 +1434,7 @@ define signext i32 @rotl_32_mask_shared(i32 signext %a, i32 signext %b, i32 sign
; RV64XTHEADBB-LABEL: rotl_32_mask_shared:
; RV64XTHEADBB: # %bb.0:
; RV64XTHEADBB-NEXT: sllw a3, a0, a2
-; RV64XTHEADBB-NEXT: neg a4, a2
+; RV64XTHEADBB-NEXT: negw a4, a2
; RV64XTHEADBB-NEXT: srlw a0, a0, a4
; RV64XTHEADBB-NEXT: or a0, a3, a0
; RV64XTHEADBB-NEXT: sllw a1, a1, a2
@@ -1600,11 +1599,10 @@ define signext i64 @rotl_64_mask_shared(i64 signext %a, i64 signext %b, i64 sign
;
; RV64XTHEADBB-LABEL: rotl_64_mask_shared:
; RV64XTHEADBB: # %bb.0:
-; RV64XTHEADBB-NEXT: andi a3, a2, 63
-; RV64XTHEADBB-NEXT: sll a4, a0, a3
-; RV64XTHEADBB-NEXT: neg a3, a3
-; RV64XTHEADBB-NEXT: srl a0, a0, a3
-; RV64XTHEADBB-NEXT: or a0, a4, a0
+; RV64XTHEADBB-NEXT: sll a3, a0, a2
+; RV64XTHEADBB-NEXT: negw a4, a2
+; RV64XTHEADBB-NEXT: srl a0, a0, a4
+; RV64XTHEADBB-NEXT: or a0, a3, a0
; RV64XTHEADBB-NEXT: sll a1, a1, a2
; RV64XTHEADBB-NEXT: add a0, a0, a1
; RV64XTHEADBB-NEXT: ret
@@ -1653,11 +1651,10 @@ define signext i32 @rotr_32_mask_shared(i32 signext %a, i32 signext %b, i32 sign
;
; RV32XTHEADBB-LABEL: rotr_32_mask_shared:
; RV32XTHEADBB: # %bb.0:
-; RV32XTHEADBB-NEXT: andi a3, a2, 31
-; RV32XTHEADBB-NEXT: srl a4, a0, a3
-; RV32XTHEADBB-NEXT: neg a3, a3
-; RV32XTHEADBB-NEXT: sll a0, a0, a3
-; RV32XTHEADBB-NEXT: or a0, a4, a0
+; RV32XTHEADBB-NEXT: srl a3, a0, a2
+; RV32XTHEADBB-NEXT: neg a4, a2
+; RV32XTHEADBB-NEXT: sll a0, a0, a4
+; RV32XTHEADBB-NEXT: or a0, a3, a0
; RV32XTHEADBB-NEXT: sll a1, a1, a2
; RV32XTHEADBB-NEXT: add a0, a0, a1
; RV32XTHEADBB-NEXT: ret
@@ -1665,7 +1662,7 @@ define signext i32 @rotr_32_mask_shared(i32 signext %a, i32 signext %b, i32 sign
; RV64XTHEADBB-LABEL: rotr_32_mask_shared:
; RV64XTHEADBB: # %bb.0:
; RV64XTHEADBB-NEXT: srlw a3, a0, a2
-; RV64XTHEADBB-NEXT: neg a4, a2
+; RV64XTHEADBB-NEXT: negw a4, a2
; RV64XTHEADBB-NEXT: sllw a0, a0, a4
; RV64XTHEADBB-NEXT: or a0, a3, a0
; RV64XTHEADBB-NEXT: sllw a1, a1, a2
@@ -1828,11 +1825,10 @@ define signext i64 @rotr_64_mask_shared(i64 signext %a, i64 signext %b, i64 sign
;
; RV64XTHEADBB-LABEL: rotr_64_mask_shared:
; RV64XTHEADBB: # %bb.0:
-; RV64XTHEADBB-NEXT: andi a3, a2, 63
-; RV64XTHEADBB-NEXT: srl a4, a0, a3
-; RV64XTHEADBB-NEXT: neg a3, a3
-; RV64XTHEADBB-NEXT: sll a0, a0, a3
-; RV64XTHEADBB-NEXT: or a0, a4, a0
+; RV64XTHEADBB-NEXT: srl a3, a0, a2
+; RV64XTHEADBB-NEXT: negw a4, a2
+; RV64XTHEADBB-NEXT: sll a0, a0, a4
+; RV64XTHEADBB-NEXT: or a0, a3, a0
; RV64XTHEADBB-NEXT: sll a1, a1, a2
; RV64XTHEADBB-NEXT: add a0, a0, a1
; RV64XTHEADBB-NEXT: ret
@@ -1885,7 +1881,6 @@ define signext i32 @rotl_32_mask_multiple(i32 signext %a, i32 signext %b, i32 si
;
; RV32XTHEADBB-LABEL: rotl_32_mask_multiple:
; RV32XTHEADBB: # %bb.0:
-; RV32XTHEADBB-NEXT: andi a2, a2, 31
; RV32XTHEADBB-NEXT: sll a3, a0, a2
; RV32XTHEADBB-NEXT: neg a4, a2
; RV32XTHEADBB-NEXT: srl a0, a0, a4
@@ -1898,9 +1893,8 @@ define signext i32 @rotl_32_mask_multiple(i32 signext %a, i32 signext %b, i32 si
;
; RV64XTHEADBB-LABEL: rotl_32_mask_multiple:
; RV64XTHEADBB: # %bb.0:
-; RV64XTHEADBB-NEXT: andi a2, a2, 31
; RV64XTHEADBB-NEXT: sllw a3, a0, a2
-; RV64XTHEADBB-NEXT: neg a4, a2
+; RV64XTHEADBB-NEXT: negw a4, a2
; RV64XTHEADBB-NEXT: srlw a0, a0, a4
; RV64XTHEADBB-NEXT: or a0, a3, a0
; RV64XTHEADBB-NEXT: sllw a2, a1, a2
@@ -2071,9 +2065,8 @@ define i64 @rotl_64_mask_multiple(i64 %a, i64 %b, i64 %amt) nounwind {
;
; RV64XTHEADBB-LABEL: rotl_64_mask_multiple:
; RV64XTHEADBB: # %bb.0:
-; RV64XTHEADBB-NEXT: andi a2, a2, 63
; RV64XTHEADBB-NEXT: sll a3, a0, a2
-; RV64XTHEADBB-NEXT: neg a4, a2
+; RV64XTHEADBB-NEXT: negw a4, a2
; RV64XTHEADBB-NEXT: srl a0, a0, a4
; RV64XTHEADBB-NEXT: or a0, a3, a0
; RV64XTHEADBB-NEXT: sll a2, a1, a2
@@ -2129,7 +2122,6 @@ define signext i32 @rotr_32_mask_multiple(i32 signext %a, i32 signext %b, i32 si
;
; RV32XTHEADBB-LABEL: rotr_32_mask_multiple:
; RV32XTHEADBB: # %bb.0:
-; RV32XTHEADBB-NEXT: andi a2, a2, 31
; RV32XTHEADBB-NEXT: srl a3, a0, a2
; RV32XTHEADBB-NEXT: neg a4, a2
; RV32XTHEADBB-NEXT: sll a0, a0, a4
@@ -2142,9 +2134,8 @@ define signext i32 @rotr_32_mask_multiple(i32 signext %a, i32 signext %b, i32 si
;
; RV64XTHEADBB-LABEL: rotr_32_mask_multiple:
; RV64XTHEADBB: # %bb.0:
-; RV64XTHEADBB-NEXT: andi a2, a2, 31
; RV64XTHEADBB-NEXT: srlw a3, a0, a2
-; RV64XTHEADBB-NEXT: neg a4, a2
+; RV64XTHEADBB-NEXT: negw a4, a2
; RV64XTHEADBB-NEXT: sllw a0, a0, a4
; RV64XTHEADBB-NEXT: or a0, a3, a0
; RV64XTHEADBB-NEXT: srlw a2, a1, a2
@@ -2313,9 +2304,8 @@ define i64 @rotr_64_mask_multiple(i64 %a, i64 %b, i64 %amt) nounwind {
;
; RV64XTHEADBB-LABEL: rotr_64_mask_multiple:
; RV64XTHEADBB: # %bb.0:
-; RV64XTHEADBB-NEXT: andi a2, a2, 63
; RV64XTHEADBB-NEXT: srl a3, a0, a2
-; RV64XTHEADBB-NEXT: neg a4, a2
+; RV64XTHEADBB-NEXT: negw a4, a2
; RV64XTHEADBB-NEXT: sll a0, a0, a4
; RV64XTHEADBB-NEXT: or a0, a3, a0
; RV64XTHEADBB-NEXT: srl a2, a1, a2
@@ -2467,7 +2457,7 @@ define i64 @rotl_64_zext(i64 %x, i32 %y) nounwind {
; RV64XTHEADBB-LABEL: rotl_64_zext:
; RV64XTHEADBB: # %bb.0:
; RV64XTHEADBB-NEXT: sll a2, a0, a1
-; RV64XTHEADBB-NEXT: neg a1, a1
+; RV64XTHEADBB-NEXT: negw a1, a1
; RV64XTHEADBB-NEXT: srl a0, a0, a1
; RV64XTHEADBB-NEXT: or a0, a2, a0
; RV64XTHEADBB-NEXT: ret
@@ -2617,7 +2607,7 @@ define i64 @rotr_64_zext(i64 %x, i32 %y) nounwind {
; RV64XTHEADBB-LABEL: rotr_64_zext:
; RV64XTHEADBB: # %bb.0:
; RV64XTHEADBB-NEXT: srl a2, a0, a1
-; RV64XTHEADBB-NEXT: neg a1, a1
+; RV64XTHEADBB-NEXT: negw a1, a1
; RV64XTHEADBB-NEXT: sll a0, a0, a1
; RV64XTHEADBB-NEXT: or a0, a2, a0
; RV64XTHEADBB-NEXT: ret
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