[PATCH] D150991: [LV] Use Legal::isUniform to detect uniform pointers.

Ayal Zaks via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue May 23 11:33:35 PDT 2023

Ayal added a comment.

Good catch!

Thinking if this may call for an alternative fix within isVectorizedMemAccessUse(), which admittedly does not affect AArch64/sve-inv-store.ll(?)

Comment at: llvm/lib/Transforms/Vectorize/LoopVectorize.cpp:4709
     return getLoadStorePointerOperand(I) == Ptr && isUniformDecision(I, VF) &&
            GetStoredValue() != Ptr;
How about the above alternative change? Seems more inline with isVectorizedMemAccessUse's documentation.
While we're here, an early exit seems simpler:
  if (isa<StoreInst>(I) && I->getOperand(0) == Ptr)
    return false;

Comment at: llvm/lib/Transforms/Vectorize/LoopVectorize.cpp:4760
       if (isVectorizedMemAccessUse(&I, Ptr)) {
         assert(isUniformDecision(&I, VF) && "consistency check");
This assert is currently redundant, and needs to be dropped (along with {}) in the alternative fix above.

Comment at: llvm/test/Transforms/LoopVectorize/AArch64/sve-inv-store.ll:173
 ; CHECK-NEXT:    [[TMP16:%.*]] = extractelement <vscale x 4 x i64> [[TMP7]], i32 [[TMP15]]
-; CHECK-NEXT:    [[TMP17:%.*]] = extractelement <vscale x 4 x ptr> [[DOTSPLAT2]], i32 0
-; CHECK-NEXT:    store i64 [[TMP16]], ptr [[TMP17]], align 1
-; CHECK-NEXT:    [[TMP18:%.*]] = call i64 @llvm.vscale.i64()
-; CHECK-NEXT:    [[TMP19:%.*]] = mul i64 [[TMP18]], 4
-; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP19]]
-; CHECK-NEXT:    [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
-; CHECK-NEXT:    br i1 [[TMP20]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]
+; CHECK-NEXT:    store i64 [[TMP16]], ptr [[TMP12]], align 1
+; CHECK-NEXT:    [[TMP17:%.*]] = call i64 @llvm.vscale.i64()
note: store to invariant address: insert-element - extract-element redundancy elimination

Comment at: llvm/test/Transforms/LoopVectorize/skeleton-lcssa-crash.ll:54
+; CHECK-NEXT:    [[TMP8:%.*]] = extractelement <2 x i16> [[WIDE_LOAD]], i32 1
 ; CHECK-NEXT:    store i16 [[TMP8]], ptr [[TMP7]], align 2, !alias.scope !3, !noalias !0
 ; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
note: store to invariant address - store-after-store redundancy elimination.

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