[PATCH] D151212: [RISCV][InsertVSETVLI] Support constant VLs larger than immediate encoding

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue May 23 09:56:41 PDT 2023


craig.topper added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll:12509
 ; RV64ZVE32F-NEXT:    lbu a2, 0(a2)
 ; RV64ZVE32F-NEXT:    li a3, 32
 ; RV64ZVE32F-NEXT:    vmv.s.x v12, a2
----------------
Is this instruction dead? Do we need to try to delete these `li` instructions or run DCE after vsetvli?


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  https://reviews.llvm.org/D151212/new/

https://reviews.llvm.org/D151212



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