[PATCH] D150316: [AArch64][InstCombine] Don't scalarize for bitselet instructions

[Nikita Popov via Phabricator via llvm-commits]

nikic added a comment.

I don't have the necessary context here, but if limiting this to not insert extra instructions works, that sounds reasonable. If we do need target cost-modelling, the transform should be moved into VectorCombine.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D150316/new/

https://reviews.llvm.org/D150316