[llvm] 033690f - [RISCV] Make zfbfmin imply the F extension

[Alex Bradbury via llvm-commits]

Author: Alex Bradbury
Date: 2023-05-23T10:10:11+01:00
New Revision: 033690fffe8f1e2f4be100ee4da62e5c04655e4f

URL: https://github.com/llvm/llvm-project/commit/033690fffe8f1e2f4be100ee4da62e5c04655e4f
DIFF: https://github.com/llvm/llvm-project/commit/033690fffe8f1e2f4be100ee4da62e5c04655e4f.diff

LOG: [RISCV] Make zfbfmin imply the F extension

Our current approach is that if one extension requires another, we make
LLVM treat it as implied. My initial zfbfmin patch failed to do this for
the F extension (documented as a requirement of zfbfmin). This patch
fixes that.

Differential Revision: https://reviews.llvm.org/D151096

Added: 
    

Modified: 
    llvm/lib/Support/RISCVISAInfo.cpp
    llvm/test/MC/RISCV/attribute-arch.s

Removed: 
    


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diff  --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
index 0307bccacd9fc..c5b42840b6881 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -923,6 +923,7 @@ static const char *ImpliedExtsZcmp[] = {"zca"};
 static const char *ImpliedExtsZcmt[] = {"zca"};
 static const char *ImpliedExtsZdinx[] = {"zfinx"};
 static const char *ImpliedExtsZfa[] = {"f"};
+static const char *ImpliedExtsZfbfmin[] = {"f"};
 static const char *ImpliedExtsZfh[] = {"f"};
 static const char *ImpliedExtsZfhmin[] = {"f"};
 static const char *ImpliedExtsZfinx[] = {"zicsr"};
@@ -984,6 +985,7 @@ static constexpr ImpliedExtsEntry ImpliedExts[] = {
     {{"zcmt"}, {ImpliedExtsZcmt}},
     {{"zdinx"}, {ImpliedExtsZdinx}},
     {{"zfa"}, {ImpliedExtsZfa}},
+    {{"zfbfmin"}, {ImpliedExtsZfbfmin}},
     {{"zfh"}, {ImpliedExtsZfh}},
     {{"zfhmin"}, {ImpliedExtsZfhmin}},
     {{"zfinx"}, {ImpliedExtsZfinx}},

diff  --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
index 663cc66c29bf0..eb99421e452c7 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -264,7 +264,7 @@
 .attribute arch, "rv32i_ssaia1p0"
 # CHECK: attribute      5, "rv32i2p1_ssaia1p0"
 
-.attribute arch, "rv32if_zfbfmin0p6"
+.attribute arch, "rv32i_zfbfmin0p6"
 # CHECK: .attribute     5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p6"
 
 .attribute arch, "rv32i_zvfbfmin0p6"