[PATCH] D150551: [AMDGPU] Reintroduce CC exception for non-inlined functions in Promote Alloca limits
Pierre van Houtryve via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue May 23 00:02:03 PDT 2023
This revision was automatically updated to reflect the committed changes.
Closed by commit rGf104eb6e1550: [AMDGPU] Reintroduce CC exception for non-inlined functions in Promote Alloca… (authored by Pierre-vh).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D150551/new/
https://reviews.llvm.org/D150551
Files:
llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
llvm/test/CodeGen/AMDGPU/vector-alloca-limits.ll
Index: llvm/test/CodeGen/AMDGPU/vector-alloca-limits.ll
===================================================================
--- llvm/test/CodeGen/AMDGPU/vector-alloca-limits.ll
+++ llvm/test/CodeGen/AMDGPU/vector-alloca-limits.ll
@@ -139,11 +139,26 @@
}
; OPT-LABEL: @func_alloca_9xi64_max256(
+; OPT: alloca
+; OPT-NOT: <9 x i64>
+; LIMIT32: alloca
+; LIMIT32-NOT: <9 x i64>
+define void @func_alloca_9xi64_max256(ptr addrspace(1) %out, i32 %index) #2 {
+entry:
+ %tmp = alloca [9 x i64], addrspace(5)
+ store i64 0, ptr addrspace(5) %tmp
+ %tmp1 = getelementptr [9 x i64], ptr addrspace(5) %tmp, i32 0, i32 %index
+ %tmp2 = load i64, ptr addrspace(5) %tmp1
+ store i64 %tmp2, ptr addrspace(1) %out
+ ret void
+}
+
+; OPT-LABEL: @alwaysinlined_func_alloca_9xi64_max256(
; OPT-NOT: alloca
; OPT: <9 x i64>
; LIMIT32: alloca
; LIMIT32-NOT: <9 x i64>
-define void @func_alloca_9xi64_max256(ptr addrspace(1) %out, i32 %index) #2 {
+define void @alwaysinlined_func_alloca_9xi64_max256(ptr addrspace(1) %out, i32 %index) #3 {
entry:
%tmp = alloca [9 x i64], addrspace(5)
store i64 0, ptr addrspace(5) %tmp
@@ -156,3 +171,4 @@
attributes #0 = { "amdgpu-flat-work-group-size"="1,1024" }
attributes #1 = { "amdgpu-flat-work-group-size"="1,512" }
attributes #2 = { "amdgpu-flat-work-group-size"="1,256" }
+attributes #3 = { alwaysinline "amdgpu-flat-work-group-size"="1,256" }
Index: llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+++ llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
@@ -162,7 +162,15 @@
return 128;
const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F);
- return ST.getMaxNumVGPRs(ST.getWavesPerEU(F).first);
+ unsigned MaxVGPRs = ST.getMaxNumVGPRs(ST.getWavesPerEU(F).first);
+
+ // A non-entry function has only 32 caller preserved registers.
+ // Do not promote alloca which will force spilling unless we know the function
+ // will be inlined.
+ if (!F.hasFnAttribute(Attribute::AlwaysInline) &&
+ !AMDGPU::isEntryFunctionCC(F.getCallingConv()))
+ MaxVGPRs = std::min(MaxVGPRs, 32u);
+ return MaxVGPRs;
}
} // end anonymous namespace
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