[PATCH] D76354: [RISCV][GlobalISel] Legalize types for ALU operations

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp:122
+
+  auto NewOp0 = MIRBuilder.buildAnyExt(s64, MI.getOperand(1).getReg());
+  auto NewOp1 = MIRBuilder.buildAnyExt(s64, MI.getOperand(2).getReg());
----------------
craig.topper wrote:
> craig.topper wrote:
> > This also seems wrong for the semantics of the generic IR.
> > 
> > G_SHL needs operand 1 zero extend. Operand 0 can be zero extend.
> > G_ASHR needs operand 0 sign extended and operand 0 zero extended
> > G_LSHR, G_UDIV and G_UREM needs both operands zero extended.
> > 
> > @arsenm do you agree?
> Add 1 to all of the operand numbers I wrote. I didn't account for defs.
I think you meant any extend for op 0 of G_SHL, but yes


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  https://reviews.llvm.org/D76354/new/

https://reviews.llvm.org/D76354